Chapter 2 The OS, the Computer, and User Programs Copyright © 2008

Operating Systems, by Dhananjay Dhamdhere Copyright © Introduction Fundamental Principles of OS Operation The Computer OS Interaction with the Computer and User Programs

Operating Systems, by Dhananjay Dhamdhere Copyright © Fundamental Principles of OS Operation The kernel of the OS is the collection of routines that form the core of the operating system –Implements control functions –Set of services to user programs –Exists in memory during operation of the OS An interrupt diverts the CPU to execution of the kernel code A software interrupt is used by programs to communicate their requests to the kernel

Operating Systems, by Dhananjay Dhamdhere Copyright © Fundamental Principles of OS Operation (continued) CPU has two modes of operation: –Kernel mode CPU can execute all instructions Kernel operates with CPU in this mode so that it can control computer operations –User mode CPU cannot execute instructions that could interfere with other programs or with the OS if used indiscriminately CPU is put in this mode to execute user programs

Operating Systems, by Dhananjay Dhamdhere Copyright © The Computer

Operating Systems, by Dhananjay Dhamdhere Copyright © The Computer (continued) The CPU Memory Management Unit (MMU) Memory Hierarchy Input/Output Interrupts

Operating Systems, by Dhananjay Dhamdhere Copyright © The CPU Two features of the CPU are visible to user programs or the OS: –General-purpose registers (GPRs) Also called program-accessible registers Hold data, addresses, index values, or the stack pointer during execution of a program –Control registers Contain information that controls or influences operation of the CPU Set of control registers is called the program status word (PSW)

Operating Systems, by Dhananjay Dhamdhere Copyright ©

Operating Systems, by Dhananjay Dhamdhere Copyright © The CPU (continued) CPU can operate in two modes: –Kernel mode Can execute privileged instructions OS puts CPU in kernel mode when it is executing instructions in the kernel –User mode Cannot execute privileged instructions OS puts CPU in user mode while executing user programs Mode (M) field of PSW contains 0 if CPU is in privileged mode and 1 if it is in user mode

Operating Systems, by Dhananjay Dhamdhere Copyright © State of the CPU GPRs and PSW contain the information needed to know what the CPU is doing –State of the CPU Kernel saves state of CPU when it takes away the CPU from program –When program is to be resumed, it reloads the saved CPU state into GPRs and PSW

Operating Systems, by Dhananjay Dhamdhere Copyright © Example 2.1: State of the CPU (Contd)

Operating Systems, by Dhananjay Dhamdhere Copyright © Memory Management Unit (MMU) Virtual memory is an illusion of memory that may be larger than the real memory of a computer –Implemented using noncontiguous memory allocation and the MMU CPU passes the address of data or instruction used in an instruction to MMU –It is called the logical addresses MMU translates logical address to physical address

Operating Systems, by Dhananjay Dhamdhere Copyright © Memory hierarchy The memory hierarchy provides a large and fast memory, at a low cost –It is an arrangement of several memories with different access speeds and sizes The CPU accesses only the fastest memory; i.e., the cache If a required byte is not present in the memory being accessed, it is loaded there from a slower memory

Operating Systems, by Dhananjay Dhamdhere Copyright ©

Operating Systems, by Dhananjay Dhamdhere Copyright © Memory Hierarchy (continued) When CPU performs a cache lookup, a cache hit or miss may occur –Hit ratio (h) of the cache is the fraction of bytes accessed by the CPU that score a hit in the cache t ema = h × t cache + (1 – h) × (t tra + t cache ) = t cache + (1 – h) × t tra where t ema = effective memory access time, t cache = access time of cache, and t tra = time taken to transfer a cache block from memory to cache.

Operating Systems, by Dhananjay Dhamdhere Copyright © Memory Hierarchy (continued) Operation of memory is analogous to operation of a cache –Blocks of bytes (pages) are transferred from disk to memory or from memory to disk –But, Memory management and transfer of blocks between memory and disk are performed by SW In the cache, the transfer is performed by HW Memory hierarchy comprising MMU, memory, and the disk is called the virtual memory

Operating Systems, by Dhananjay Dhamdhere Copyright © Memory Hierarchy (continued) Memory protection is implemented by checking whether a memory address used by a program lies outside the memory area allocated to it –Control registers used: base and size (also called limit) –Address of first byte = –Address of last byte = + – 1

Operating Systems, by Dhananjay Dhamdhere Copyright © Example 2.2: Basics of Memory Protection interrupt Execution of Load instruction causes protection violation

Operating Systems, by Dhananjay Dhamdhere Copyright © Input/Output

Operating Systems, by Dhananjay Dhamdhere Copyright © Interrupts An event is a situation that requires OS’s attention –Designer associates an interrupt with each event Purpose is to report occurrence of the event to OS and enable it to perform event handling actions Interrupt action saves CPU state and loads new contents into the PSW and GPRs –CPU starts executing instructions of an interrupt servicing routine (ISR) in the kernel

Operating Systems, by Dhananjay Dhamdhere Copyright © Interrupts (continued)

Operating Systems, by Dhananjay Dhamdhere Copyright ©

Operating Systems, by Dhananjay Dhamdhere Copyright © OS Interaction with the Computer and User Programs OS interacts with the computer to –know information about events, so that it can service them –restore CPU state to resume a program after servicing an interrupt Programs need to use services of the OS for purposes such as initiating an I/O operation –The method to cause an interrupt and pass requirement to the OS is known as a System call Will learn about: –Controlling Execution of Programs –Interrupt Servicing –System Calls

Operating Systems, by Dhananjay Dhamdhere Copyright © Controlling Execution of Programs 1.When user program starts, PSW should contain: a.Program counter (PC) field b.Mode (M) field, set to user mode (1) c.Memory protection information (MPI) field contains start address in memory and size of program d.Interrupt mask (IM) field, set to enable interrupts 2.When program is interrupted, CPU state (PSW and GPRs) are saved Program table or process control block (PCB) 3.When program is resumed, its CPU state is restored

Operating Systems, by Dhananjay Dhamdhere Copyright © Interrupt Servicing Context save saves CPU state of the program The scheduler selects a a program for execution

Operating Systems, by Dhananjay Dhamdhere Copyright © Interrupt Servicing (continued)

Operating Systems, by Dhananjay Dhamdhere Copyright © Interrupt Servicing (continued) Two approaches for nested interrupt servicing: –Disable nested interrupts through masking –Handle nested interrupts─preemptible kernel

Operating Systems, by Dhananjay Dhamdhere Copyright © System Calls

Operating Systems, by Dhananjay Dhamdhere Copyright © Example 2.4: System Call in a Hypothetical OS CPU provides the SI instruction to cause a software interrupt OS provides system call for obtaining current time –Code is 78: Instruction SI 78 causes a SW interrupt 78 is entered in IC field of PSW before it is saved Interrupt vector for program contains aaa in PC –CPU is switched to routine with start address aaa –It finds that IC is 78 and determines that program needs time of day Time is returned to program in a standard location, typically a data register

Operating Systems, by Dhananjay Dhamdhere Copyright © System Calls (continued)

Operating Systems, by Dhananjay Dhamdhere Copyright © Summary An interrupt is a special signal sent to CPU to indicate occurrence of an event –It transfers control to the OS –A system call is a SW interrupt A program uses it to request OS services CPU’s control registers govern its functioning –Program status word (PSW) is the collection of these OS kernel saves CPU state when interrupt occurs –i.e., PSW and GPRs CPU has two modes of operation controlled by mode (M) field of PSW –User mode and kernel mode

Operating Systems, by Dhananjay Dhamdhere Copyright © Summary (continued) Memory hierarchy provides the same effect as a fast and large memory, at a low cost –Contains: A very fast and small cache memory A slower and larger RAM A disk Effective memory access time depends on cache hit ratio I/O system uses direct memory access (DMA) to permit CPU and I/O system to operate independently