SDDEC1004 H IGH S PEED W IRED D ATA C OLLECTION Honeywell Bob Dearth Michael Retzler Brad Lucht ISU Prof. Zhengdao Wang Zachary Coffin, Cpr E Radell Young, E E William Zimmerman, E E*

R EQUIREMENTS / S PECIFICATION P ROBLEM / N EED S TATEMENT Honeywell’s Kansas City Plant needs a method to collect experimental data very quickly over a distance of 300 feet. All previous designs are now too slow and error-prone to collect useful data.

R EQUIREMENTS /S PECIFICATION C ONCEPT D ESCRIPTION Transmitter and Receiver Commercial Off-the-Shelf Components Speed requirements Cost constraints Availability Cat-5e Frequency Response Availability and Cost Onboard Battery

C ONCEPT B LOCK D IAGRAM

R EQUIREMENTS /S PECIFICATION O PERATING E NVIRONMENT Equipment shall be used indoors in a regulated testing environment. Transmitter shall be housed in a larger device, in a cavity no larger than 3x3x1/2 inches. Nature of experiments inhibits wireless communication. Data is to be retrieved on a Windows XP machine.

R EQUIREMENTS /S PECIFICATION U SER I NTERFACE D ESCRIPTION Data shall be made available in a table format on a Windows XP computer There may be an optional power indicator LED on the transmitter board

R EQUIREMENTS /S PECIFICATION F UNCTIONAL R EQUIREMENTS Convert four analog voltage signals from provided piezoelectric sensors to 8-bit digital signals at a minimum rate of 2 million samples per second Data collection and transmission must start from a time approximately T-4 second, and end no earlier than T-5us System shall use wired connection Maximum Voltage Supply 24V DC Minimize error

R EQUIREMENTS /S PECIFICATION N ON -F UNCTIONAL R EQUIREMENTS Budget $100 per transmitter Transmitting device shall be no larger than 3x3x½ inches in volume

R EQUIREMENTS /S PECIFICATION M ARKET / L ITERATURE S URVEY Chipset optimized for performance at target price All-in-one chips too expensive and too high latency Cable specified for availability and cost considerations

R EQUIREMENTS /S PECIFICATION D ELIVERABLES Chipset meeting all design requirements (cost, size, performance) Schematic has been created in Cadence Footprints for some chips were not provided in datasheets – this delayed PCB generation

P ROJECT P LAN : W ORK B REAKDOWN – C ONTRIBUTION BY MEMBER TaskZCRYMMBZ Chipset Specification50%45%5% Documentation30%70% Schematics100% Testing40% 20% Poster45%55%

P ROJECT P LAN : R ESOURCE R EQUIREMENTS Manufacturing equipment to produce hundreds of transmitter boards Sensors and appropriate biasing circuitry as analog input sources Windows XP data capture environment

P ROJECT P LAN : P ROJECT S CHEDULE

P ROJECT P LAN : R ISKS Loss of team member – Mazdi Masud New team member – Bill Zimmerman Signal loss too great Specify more robust cable – Shielded Cat-6 On-board latency too great Add clocked register between multiplexers and LVDS

S YSTEM D ESIGN S YSTEM R EQUIREMENTS / A NALYSIS PCB layout to connect chips as necessary No less than 3.3V energy source A combination of several button cell batteries may provide a more cost-effective solution than standard 9V cells

S YSTEM D ESIGN F UNCTIONAL D ECOMPOSITION Transmitter board Accepts four voltage signals (current version takes a range of -150 to +150 Volts, as specified by piezo sensor) Applies 1-bit odd parity to each channel Transmits over four channels (three data, one clock, eight conductors) in LVDS Receiver board Regenerates clock signal Decodes LVDS data and sends to USB UART Windows XP Aligns data samples to satisfy parity check

D ETAILED D ESIGN HW/SW S PECIFICATIONS – C HIPSET Measurement Specialties, - Inc. LDT 1-028K/L (Piezo, 4x) Texas Instruments - TPS76918DBVR (Voltage Regulator, 2x) Texas Instruments - TPS76933DBVR (Voltage Regulator, 2x) Texas Instruments - ADS931E (AtoD, 4x) Texas Instruments - CD74AC280M96 (Parity, 4x) Texas Instruments - ADG706BRUZ (MUX, 3x) ECS Inc. - ECS X (24MHz Crystal) Texas Instruments - CDCE913PW (Clock Generator, 2x) Texas Instruments - CD74HCT163E (Counter) National Semiconductor - DS92LV040ATLQA (LVDS Transceiver, 2x) ST Ericsson - ISP1506ABS (USB Transceiver) Fairchild Semiconductor - 74VHC04MX (Inverters) Texas Instruments - SN74LV27ADR (NOR gates)

D ETAILED D ESIGN I/O S PECIFICATIONS The individual sample bits are transmitted in the following 12-bit pattern: Where 8-bit samples A through D consist of bits 0 through 7 and parity bit ‘P’. Time (sec)Channel 1 bitChannel 2 bitChannel 3 bitChannel 4 bit 0A0B0C0(Clock) E-08A1B1C1(Clock) E-08A2B2C2(Clock) A3B3C3(Clock) E-07A4B4C4(Clock) E-07A5B5C5(Clock) A6B6C6(Clock) E-07A7B7C7(Clock) E-07APBPCP(Clock) D0D3D6(Clock) E-07D1D4D7(Clock) E-07D2D5DP(Clock)

D ETAILED D ESIGN U SER I NTERFACE S PECIFICATION Once the transmitter board is powered it will continuously transmit data – no interaction required. Data may be collected from the UART as desired

D ETAILED D ESIGN T EST P LAN Testing specifications received from Honeywell Input square waves of frequencies up to 1MHz Signal input to LVDS transmitter must not waver during one clock period due to MUX propagation delay If it does, signal buffer will be required, increasing latency, cost, size, and requiring a different PCB

D ETAILED D ESIGN S IMULATION / P ROTOTYPING Complexity of the system prevented simulation Prototype construction is taking longer than anticipated

P ROTOTYPE B UILD PCB design could not be finalized before receiving chipset Some datasheets did not include device dimensions Second loss of team member reduced available man-hours dedicated to project Obtained chipset, sensors, cable, and final schematic

P ROTOTYPE T EST R ESULTS Typical sensors (supplied by Honeywell) deliver ±150V 300ft of Cat-5e cable was tested for crosstalk and signal degradation Signal loss measured as -10dB at 24MHz Cross-talk measured minimal

P ROTOTYPE T EST R ESULTS Piezo sensor test results Voltage measured at 50 attenuation factor Cat-5 Cable test results Frequency response similar for distinct pairs Crosstalk very low for all pairs

P ROJECT C LOSURE C ONCLUSIONS / L ESSONS L EARNED Be Proactive Team members may be motivated by the activities of others Follow a Design Process After a process is selected tasks can more easily be distributed amongst team members Stay Positive Perform to the best of your abilities

P ROJECT C LOSURE F UTURE W ORK PCB must be completed based on measurements of chip dimensions Chips and interface jacks must then be soldered Software to decode data stream Align data samples to satisfy parity check

P ROJECT S UCCESS – D EMO (S CHEMATIC )

P ROJECT S UCCESS I NNOVATION Multiple transmission methods were investigated in order to determine the best method of achieving success within constraints set by Honeywell. Methods considered include: QAM and coaxial cable Simple Low Voltage Differential Signaling (LVDS) and twisted pairs (category-5) cable LVDS Multi Level Transmitting 4-levels (MLT-4) and Non Return to Zero Inverting (NRZ-I), again with cat-5 cable

Q UESTIONS