ECE Synthesis & Verification, Lecture 17 1 ECE 697B (667) Spring 2006 ECE 697B (667) Spring 2006 Synthesis and Verification of Digital Systems Technology Mapping II (binate covering) Slides adapted (with permission) from A. Kuehlmann, UC Berkeley 2003

ECE Synthesis & Verification, Lecture 172 DAG Covering as Binate Covering Problem Compute all possible matches {m k } for each node Using a variable m i for each match of a pattern graph in the subject graph, (m i = 1 if match is chosen; m i = 0 otherwise) Write a clause for each node of the subject graph indicating which matches cover this node. Each node has to be covered. –e.g., if a subject node is covered by matches {m 2, m 5, m 10 }, then the clause would be (m 2 + m 5 + m 10 ). Repeat for each subject node and take the product over all subject nodes (CNF). m 1 m 2... m k n1n2...nln1n2...nl nodes

ECE Synthesis & Verification, Lecture 173 DAG Covering as Binate Covering Problem Any satisfying assignment guarantees that all subject nodes are covered, but It does not guarantee that other matches create outputs needed as inputs for a given match (legal covering). Rectify this by adding additional clauses. not an output of a chosen match

ECE Synthesis & Verification, Lecture 174 DAG Covering as Binate Covering Problem Let match m i have subject nodes s i1,…,s in as inputs. If m i is chosen, one of the matches that realizes s ij must also be chosen for each intermediate input j Let S ij be the disjunctive expression in the variables m k giving the possible matches which realize s ij as an output node. Selecting match m i implies satisfying each of the expressions S ij for j = 1 … n. This can be written as: ( m i  (S i1 … S in ) )  (  m i + (S i1 … S in ) )  ((  m i + S i1 ) … (  m i + S in ) ) mimi s i1 s ij s in

ECE Synthesis & Verification, Lecture 175 DAG Covering as Binate Covering Problem Also, one of the matches for each primary output of the circuit must be selected. An assignment of values to variables m i that satisfies the above covering expression is a legal graph cover. For area optimization, each match m i has a cost c i : the area of the gate the match represents. The goal is a satisfying assignment with the least total cost. –Find a least-cost prime: if a variable m i = 0 its cost is 0, else its cost is c i m i = 1 means that match i is chosen m i = 0 means that match i is not chosen

ECE Synthesis & Verification, Lecture 176 Binate Covering This problem is more general than unate covering for two-level minimization because –variables are present in the covering expression in both their true and complemented forms. The covering expression is a binate logic function, and the problem is referred to as the binate covering problem.

ECE Synthesis & Verification, Lecture 177 Binate Covering: Example Gate Cost Inputs Produces Covers m 1 inv 1 b g 1 g 1 m 2 1 a g 2 g 2 m 3 nand2 2 g 1, g 2 g 3 g 3 m 4 nand2 2 a,b g 4 g 4 m 5 2 g 3, g 4 g 5 g 5 m 6 inv 1 g 4 g 6 g 6 m 7 nand2 2 g 6,c g 7 g 7 m 8 inv 1 g 7 g 8 g 8 m 9 nand2 2 g 8,d g 9 g 9 m 10 nand3 3 g 6,c,d g 9 g 7, g 8 9 m 11 nand3 3 a, b, c g 7 g 4, g 6 7 m 12 xnor2 5 a,b g 5 g 1, g m nand44 a, b, c,d g g, g m 14 oai21 3 a, b,g 4 g 5 g 1, g d a b c o1o1 o2o2 m 13 m 12 m 14 m 10 m 11

ECE Synthesis & Verification, Lecture 178 Binate Covering: Example Generate constraints that each node g i be covered by some match. (m 1 + m 12 + m 14 ) (m 2 + m 12 + m 14 ) (m 3 + m 12 + m 14 )(m 4 + m 11 + m 12 + m 13 ) (m 5 + m 12 + m 14 )(m 6 + m 11 + m 13 ) (m 7 + m 10 + m 11 + m 13 ) (m 8 + m 10 + m 13 ) (m 9 + m 10 + m 13 ) d a b c o1o1 o2o2 m 13 m 12 m 14 m 10 m 11 To ensure that a cover leads to a valid circuit, extra clauses are generated. For example, selecting m 3 requires that: a match be chosen which produces g 2 as an output, and a match be chosen which produces g 1 as an output. The only match which produces g 1 is m 1 ; same for g 2 and m 2, etc.

ECE Synthesis & Verification, Lecture 179 Binate Covering: Example The primary output nodes g 5 and g 9 must be realized as an output of some match. –The matches which realize g 5 as an output are m 5, m 12, m 14 ; –The matches which realize g 9 as an output are m 9, m 10, m 13 Note: –A match which requires a primary input as an input is satisfied trivially. –Matches m 1,m 2,m 4,m 11,m 12,m 13 are driven only by primary inputs and do not require additional clauses d a b c o1o1 o2o2 m 13 m 12 m 14 m 10 m 11

ECE Synthesis & Verification, Lecture 1710 Binate Covering: Example Finally, we get: (  m 3 + m 1 ) (  m 3 + m 2 ) (  m 5 + m 3 +) (  m 5 + m 4 ) (  m 6 + m 4 ) (  m 7 + m 6 ) (  m 8 + m 7 ) (  m 9 + m 8 ) (  m 10 + m 6 ) (  m 14 + m 4 ) (m 5 + m 12 + m 14 ) (m 9 + m 10 + m 13 ) The covering expression has 58 implicants The least cost prime implicant is  m 3  m 5  m 6  m 7  m 8  m 9  m 10  m 11 m 12 m 13  m 14 This uses two gates for a cost of nine gate units, for matches: m 12 (xor2) and m 13 (nand4).

ECE Synthesis & Verification, Lecture 1711 Gate Cost Inputs Produces Covers m 1 inv 1 b g 1 g 1 m 2 1 a g 2 g 2 m 3 nand2 2 g 1, g 2 g 3 g 3 m 4 nand2 2 a,b g 4 g 4 m 5 2 g 3, g 4 g 5 g 5 m 6 inv 1 g 4 g 6 g 6 m 7 nand2 2 g 6,c g 7 g 7 m 8 inv 1 g 7 g 8 g 8 m 9 nand2 2 g 8,d g 9 g 9 m 10 nand3 3 g 6,c,d g 9 g 7, g 8 9 m 11 nand3 3 a, b, c g 7 g 4, g 6 7 m 12 xnor2 5 a,b g 5 g 1, g m 13 nand4 4 a, b, c,d g 9 g 4, g m 14 oai21 3 a, b,g 4 g 5 g 1, g  m 3  m 5  m 6  m 7  m 8  m 9  m 10  m 11 m 12 m 13  m a b c d o1o1 o2o2 Note that the node g 4 is covered by both matches m 12 m 13

ECE Synthesis & Verification, Lecture 1712 Complexity of DAG covering More general than unate covering For unate covering, finding a feasible solution is easy Finding least cost prime of a binate function is NP hard Even finding a feasible solution is NP-complete (SAT). DAG-covering: covering + implication constraints Given a subject graph, the binate covering provides the exact solution to the technology-mapping problem. –However, better results may be obtained with a different initial decomposition into 2-input NANDS and inverters Methods to solve the binate covering problem : –Branch and bound [Thelen] –BDD-based [Lin and Somenzi] –use Constrained Programming methods [open problem] Even for moderate-size networks, these are expensive.

ECE Synthesis & Verification, Lecture 1713 Summary Two approaches to technology mapping –DAG (tree) covering –Binate mapping New approaches: combined logic decomposition and technology mapping –Lehman, Watanabe allgorithm [1994] –Efficiently encode a set on AND2/INV decompositions –Dynamically perform logic decomposition –Was implemented and used for commercial design projects (DEC/Compaq Alpha) Technology mapping for FPGAs –simpler, can be done during functional decomposition –directly on a BDD