October 18, 2001Cho & Kim 1 Software Synthesis EE202A Presentation October 18, 2001 Young H. Cho and Seung Hyun Kim

October 18, 2001Cho & Kim 2 Outline  Background  HW/SW Co-design  Software Synthesis  Summary

October 18, 2001Cho & Kim 3 Background  Embedded Software  Constrained Structure  “Simple,” Multiple Tasks  Target Architecture

October 18, 2001Cho & Kim 4 HW/SW Co-design  Reactive Real-time System  Mixed HW/SW System  Software – Flexibility  Hardware – Performance

October 18, 2001Cho & Kim 5 HW/SW Co-Design Formal Languages Partitioning HW SynthesisSW Synthesis RTOSTasksLogic Synthesis Code OptimizationLogic Optimization Board Level Prototyping Co-Simulation And Formal Verification

October 18, 2001Cho & Kim 6 Partitioning High-Level Design  Formal Languages  Textual Representation  Graphical Representation  Design Partitioning  Platform Resource  HW/SW Synthesis A B C

October 18, 2001Cho & Kim 7 Software Synthesis  Goal: Optimized software from high-level specification  Issues to consider  Target hardware support  Retargetable compilers  Result: Efficient code for the target processor A B C begin X1=TaskA(W); X2=TaskA(W); Y=TaskB(X1); result=TaskC(X2,Y); end

October 18, 2001Cho & Kim 8 Code Generation  Static Code  Static (object) code for each tasks  Library of inline codes  Code optimization  Task Handling  Resource management  Static/dynamic scheduling  Communication

October 18, 2001Cho & Kim 9 Software Synthesis Example Task B Downsample 2 to 1 Task A Upsample 1 to High-Level Description Static Code for (i=0;i<3;i++) { Out[i]=In; } Reg=In[0]+In[1]; Out=Reg>>1; main(Samples *In) { while() { /* Schedule 2A */ for (j=0;j<2;j++) { /* inline code: Task A */ for (i=0;i<3;i++) { OutA[j*3+i]=InA[j]; } for (k=0;k<3;k++) { /* inline code: Task B */ Reg=OutA[k*2] +OutA[k*2+1]; OutB[k]=Reg>>1; } Code Generation 2 (TaskA) 3 (TaskB) & Schedule

October 18, 2001Cho & Kim 10 Programming Models  FSM Model  Co-design Finite State Machine (CFSM)  Dataflow Models  Synchronous Dataflow (SDF)  Boolean Dataflow  Dynamic Dataflow  Processor Network  Others

October 18, 2001Cho & Kim 11 CFSM  Extended FSM  Globally Asynchronous Locally Synchronous (GALS)  Unbiased towards HW or SW  Reactive, control-dominated systems  Size of the systems that can be mapped

October 18, 2001Cho & Kim 12 SW Synthesis with CFSM  Software Graph (S-Graph)  Task Synthesis  Real-Time Operating System (RTOS)  Machine Code Compilation

October 18, 2001Cho & Kim 13 S-Graph  Control/Data-Flow Diagram  Directed Acyclic Graph (DAG) BEGIN present_c = 1 a = ?c a’ := 0 emit_y := 1 END a’ := a + 1a’ := a emit_y := 0 falsetrue falsetrue module simpleCFSM: input c: integer; output y; var a: integer in loop await c; if a = ?c then a := 0; emit y; else a := a + 1; end if end loop end var end module

October 18, 2001Cho & Kim 14 Task Synthesis  Construction  Translation of transition function of CFSM  Recursively built from the reactive function  Optimization  Reordering or collapsing test nodes  Code-size estimation  Translation  Target language (e.g., C code)

October 18, 2001Cho & Kim 15 RTOS  Scheduling  Individual CFSM  Communication Mechanisms  Set of flags  Memory mapped I/O port of the micro- controller  Polling or interrupts  Synthesis or Commercial RTOS

October 18, 2001Cho & Kim 16 Cost/Performance Estimation  Accurate and Quick Estimation  Code size  Min/max execution time  Considerations  Code structures  System platform  Solution  Assign cost/timing parameters

October 18, 2001Cho & Kim 17 SDF  Digital Signal Processing  Graphical Representation  Actors/Nodes  Directed edges  Delays  Synchrony  Consume Tokens  Produce Tokens  Fixed number of Tokens a b c D D

October 18, 2001Cho & Kim 18 Schedule/Memory  Static scheduling  Determine task buffer size  Memory efficient edge delay  Deterministic at compile time

October 18, 2001Cho & Kim 19 SW Synthesis with SDF  Library of actor code blocks  Determine static schedule  Optimal code size  Performance  Inline code using schedule

October 18, 2001Cho & Kim 20 Summary  HW/SW Co-design  Software Synthesis  Highly optimized code  Timing constraints  Efficient Resource Usage  Highest performance per cost  Control over implementation cost

October 18, 2001Cho & Kim 21 Related Research  Berkeley HW/SW Co-Design Group   Berkeley Ptolemy Group   CHINOOK   VULCAN  Cadence Cierto VCC  Jeckle: the JAVA ECL compiler

October 18, 2001Cho & Kim 22 References 1.A. Sangiovanni-Vincentelli, “What is software synthesis?,” Computer Design Editorial, Department of EECS, UC Berkeley, Berkeley, CA, June Berkeley POLIS Group, “A Framework for Hardware-Software Co- Design of Embedded System,” POLIS Website, Department of EECS, UC Berkeley, Berkeley, CA, F. Thoen, M. Cornero, G. Goosens, and H. DeMan, “Software synthesis for real-time information processing systems,” ACM SIGPLAN, Vol. 30, No. 11, November Linkoping University HW/SW Co-design Course Website, EE249 “Design of Embedded Systems: Models, Validations, and Synthesis,” UC Berkeley, CA P. Chou, and G. Borriello, “Software scheduling in the co-synthesis of reactive real-time systems,’ 31st ACM/IEEE Design Automation Conference, San Diego, CA, pp. 1-4, June

October 18, 2001Cho & Kim 23 References 7.E. Lee, “Embedded software,” UC Berkeley ERL Memorandum M01/26, F. Balarin, L. Lavagno, P. Murthy, and A. Sangiovanni-Vincentelli, “Scheduling for embedded real-time systems,” IEEE Design & Test of Computers, Vol. 15, No. 1, pp , January-March S. Bhattacharyya, R. Leupers, and P. Marwedel, “Software synthesis and code generation for signal processing systems,” IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, Vol. 47, No. 9, pp , September S. Bhattacharyya, P. Murthy, and E. Lee, “Synthesis of embedded software dataflow specifications,” Journal of VLSI Signal Processing Systems, Vol. 21, No. 2, pp , June 1999.