Loran-C Receiver Team Deathstar: Christopher Birschbach Matthew Hayman Matthew Anderson Christina Corner Erin Mowbray October 5, 2004 ECEN 4610 Capstone CDR

Agenda Budget Budget System Diagram System Diagram Subsystem Functionality Subsystem Functionality –Hardware/Schematics –Parts List –Software Design Progress since PDR Progress since PDR Future Goals and Deadlines Future Goals and Deadlines –Milestone 1 –Milestone 2 –Expo Division of Labor Division of Labor Questions/Comments Questions/Comments

Budget ItemDescription Estimated Price Processor$ LCD Display $75.00 Additional memory $50.00 A to D converter $50.00 Antenna Assembly $ Receiver Enclosure $ Printed Circuit Board $ FPGA Xilinx FPGA Evaluation Kit $ Filters 3 Butterworth (8th order) 3 Butterworth (8th order)$75.00 RS-232 Interface $25.00 Support Electronics Resistors, Caps, switches, sockets, cables $ Power Supply $ Student Designed User Manual Weighted Paper, Binding, Printing Costs $ Final Project Display Printed Poster for Engineering Expo $ Loran C User Handbook $25.00 Misc. (Ink Cartridges, Repair parts, reference manuals) $ TOTAL:$1,750.00

Block Diagram

Outline of Approach The system will consist of the following subsystems: The system will consist of the following subsystems: –Antenna Receiver –Analog-to-digital converter –Motorola 68HC11 processor –Memory –FPGA –Serial Interface –PC –Power

Antenna/Receiver AM Antenna 8th Order Butterworth Filter (MAX274B) (This portion of the project will continue when the filters from Maxim arrive.)

Signal Processing Unit Part List Parts ListPart Number Motorola Processor68HC11 FlashAT29C256 Bi-directional drivers74HC245 Latch74HC373 Schmitt trigger inverter74HC14 Xilinix FPGAXCS10 FPGA EPROMXC18V256 RAMHM V regulator78M33 5V regulator7805 A/D ConverterAD7828 RS-232 AdapterMAX233 TTL AND gate74LS08 8 MHz clockCO6050

Processor Schematic

FPGA Design Chip select Chip select State machine State machine Counter Counter

FPGA Schematic

FPGA – Chip Select

Software Design FPGA: FPGA: –Input Digital Loran-C signal Digital Loran-C signal –Output Counter Data Counter Data Processor: Processor: –Input Counter Data Counter Data –Output Time delays Time delays PC: PC: –Input Time delays Time delays –Output Latitudinal and Longitudinal coordinates Latitudinal and Longitudinal coordinates

Software Design Initial Test Code Initial Test Code

Software Design

Progress since PDR Schematic Design Schematic Design Initial Wire wrapped board completed Initial Wire wrapped board completed Basic Processor Functionality Basic Processor Functionality Basic FPGA Functionality Basic FPGA Functionality Basic RAM Functionality Basic RAM Functionality

Project Timeline

Future Deadlines Milestone 1 – 10/26 Milestone 1 – 10/26 Milestone 2 – 11/16 Milestone 2 – 11/16 Open-Lab Expo – 12/9 Open-Lab Expo – 12/9

Milestone 1 Date: October 26 th Date: October 26 th Parts completed: Parts completed: –Completed Wiring on Vector Board –Antenna/Filtering –Clean signal –Sampling by A/D converter completed –Order first PCB

Milestone 2 Date: November 16 th Date: November 16 th Parts Completed: Parts Completed: –Functioning PCB –State machine on FPGA working –Communication between the Processing Unit and Antenna/Receiver.

Capstone Expo Working Loran-C Receiver Working Loran-C Receiver –Functionality between all 3 Subsystems: Antenna/Receiver, Processing Unit, & PC –Working Serial Interface Interface

Extra Features These will be added if time permits at the end of the semester. These will be added if time permits at the end of the semester. –Portable Power Supply –LCD Display

Division of Labor Matt A Matt A –Power –Memory interface –Microprocessor Programming Chris B Chris B –PC programming –Microprocessor programming –User’s Manual Christy C Christy C –Antenna/Filtering –Verilog Design –User’s Manual Matt H Matt H –Antenna/Filtering –PCB –Microprocessor Programming –PC programming Erin M Erin M –Verilog Design –User’s Manual –PC interface

Questions/Comments