1. Project O.N.O.S.E. Optical Noxious Odor Sensing Electronics Capstone Critical Design Review Fall 2003

2. Team Members Chris Bauer Anubhav Bhatia Diane Cyr Jennifer Sweezey Andy White

3. Overview O.N.O.S.E. Goals System Specs Schematics/Timing Diagrams Updated Tasks Current Status Updated Schedule Updated Risks Division of Labor

4. O.N.O.S.E. Goals Provide the existing optical nose instrument with a more versatile/complete control and interface system Allow a user to accurately detect the presence and concentration of a chemical vapor Provide a useful tool for a wide range of applications, such as: military operations, homeland security, perfume testing, etc.

5. System Block Diagram PumpTransducer Optical Circuitry Phase- Locked Loop A to D Converter Processor LCD

6. System Components ClockECS-2200b 8.0 MHz MicroprocessorMC68HC000 FPGA/PROMSpartan I XCS10/ XC18V256JC EPROMAM27C512 Data Bus Drivers74HC245 Address Bus Drivers74HC244 Resistors/CapacitorsVarious sizes/values PLLTBD – analog or digital A/D and D/ATBD (at least 12-bit) LCD2x20 display Keypad9 or 12 key

7. System Schematic – Clock and Reset Circuits

8. System Schematic - Processor

9. Bus Timing - Motorola 68000

10. System Schematic - Drivers

11. Example Pin-outs Address and Data Drivers

12. System Schematic - ROM

13. Hardware Problems Encountered Faulty reset switch Various pins on processor not pulled to off state R/W line connected to inverter incorrectly Analyzer pods wired incorrectly System critical SIP removed EPROMs inserted backwards – big/little endian convention

14. Detailed Tasks Ever-present Tasks Processor Hardware Software Interfacing Functional Definition

15. Ever-present Tasks Testing at each development stage Meeting with Prof. Dana Anderson and Hongke Ye to gather technical info about existing nose instrument Interfacing our processor with the existing nose for testing Future considerations – battery power, wireless link, etc. Weekly reports, keeping up with schedule

16. Processor Hardware Tasks Reset Circuit Clock Bypass Caps Processor Bus Drivers/Pull-ups ROM (test nop-nop-nop- jmp at this point) FPGA/PROM JTAG Interface RAM RAM walkthrough test (DIP switch/LEDs for testing) Serial Port A/Ds and D/As Phase-Locked Loop LCD Keypad More components TBD

17. Software Tasks Incremental testing programs –nop-nop-nop-jmp –DIP switch/LED Read/Write test –RAM test Sniffing control – periodic signal Data collection/storage Data interpretation – sample or reference gas? Data Analysis –Provided calibration curve –Measured calibration curve –Interpolated calibration curve User Interface –LCD control –Keypad reading

18. Interfacing Tasks Gas pump control – periodic signal –Signal characteristics –Chemistry/physics limitations or concerns –How to process the reference/sample gas signals Synchronization –Phase-locked loop to keep detector signal in sync with the pump control –Analog or Digital? –Implementation Calibration Curve –Lookup table –Interpolation – how? User Interface –Keys/buttons –LCD –Serial output to PC – data file creation – plotting, etc.

19. Functional Definition Get a solid idea of what the device should do –Purpose –Applications Come up with or find out concrete specifications for inputs/outputs and how to process/interface them Determine or assume how the user will want to interact with the device Get everyone on the same page for the rest of the development process!

20. Current Status Processor wire wrapped and tested Reset and Clock circuits Functioning Address and Data Drivers wire wrapped EPROM wire wrapped NOP-NOP-NOP-JMP Executed from ROM Prepared to implement the FPGA

21. Old Schedule

22. Updated Schedule

23. Risks Risk 1: Design –Problem: Customer wants vs. needs –Solution: Team given design control Risk 2: Connection to sniffer –Problem: Assumptions –Solution: Given specifications

24. Risks Cont. Risk 3: Feedback –Problem: unknown PPM –Solution1: Given equations for feedback curve –Solution2: Access to known concentrations Risk 4: Battery Power –Problem: lack of experience with Battery power

25. Division of Responsibility Design: Team Build it –Hardware: Chris/Diane –Software: Andy/Jen Interface (Connect it): Chris/Diane Program Feedback Tables: Andy/Jen Milestone I: Team Battery: Chris/Diane/A.B.

26. Division of Responsibility cont. LCD: A.B./Andy/Jen PLL: A.B./Andy Input/Output: Team Milestone II: Team Tech. Reference Manual: A.B./Team User’s Manual: A.B./Team Research: Team

27. Costs So Far Wire Wrap Board: $ 11.83 Power Leads and Stand-offs: $ 3.66 Capacitor: $0.43 Total: $15.92

28. Questions? Jennifer – Overview, System Block Diagram A.B. – System Specs Chris – Hardware problems and tasks Andy – Software and Interfacing tasks Diane – Schedule, risks and division of labor