7/13/ EE4271 VLSI Design VLSI Routing

2 7/13/2015 Routing Problem Routing to reduce the area

3 7/13/2015 Metal layer 1 Via Routing Anatomy Top view 3D view Metal layer 2 Metal layer 3 Symbolic Layout ©Bazargan

4 7/13/2015 Routing Grid

5 7/13/2015 Channel Routing Terminology Upper boundary Lower boundary Tracks Terminals (Gate Pins) Via Width

6 7/13/2015 Channel Routing Problem - I Input: –Two vectors of the same length to represent the pins on two sides of the channel. –One horizontal layer and one vertical layer Output: –Connect pins of the same net together. –Minimize the channel width. –Minimize the number of vias.

7 7/13/2015 Channel Routing Problem - II Example: ( ) ( ) where 0 = no terminal

8 7/13/2015 A Channel Routing Example

9 7/13/2015 The Other Example

10 7/13/2015 Lower Bound on Channel Width Localdensity Channel density = Maximum local density Lower bound = 4 Lower bound on channel width = Channel density

11 7/13/2015 A More Complex Example # columns =174, # nets=72, density =19 Routing result: number of tracks=20

12 7/13/2015 Realistic Design From DAC Knowledge Center Different colors refer to different wire densities. Red color means congestion.