EE105 Fall 2007Lecture 16, Slide 1Prof. Liu, UC Berkeley Lecture 16 OUTLINE MOS capacitor (cont’d) – Effect of channel-to-body bias – Small-signal capacitance – PMOS capacitor NMOSFET in ON state – Derivation of I-V characteristics – Regions of operation Reading: Chapter ANNOUNCEMENTS Wed. discussion section (Eudean Sun) moved to 2-3PM in 293 Cory HW#9 is posted online.

EE105 Fall 2007Lecture 16, Slide 2Prof. Liu, UC Berkeley The semiconductor potential is The potential in the body (“bulk”) is At V GB = V TH, the potential at the surface is  The total potential dropped in the semiconductor is 2  B  The depletion width is V GB = V TH (Threshold) V TH is defined to be the gate voltage at which the inversion-layer carrier concentration is equal to the channel dopant concentration. – For an NMOS device, n = N A at the surface (x=0) when V GB = V TH : -t ox XdXd 0 XdXd

EE105 Fall 2007Lecture 16, Slide 3Prof. Liu, UC Berkeley Effect of Channel-to-Body Bias When a MOS device is biased in the inversion region of operation, a PN junction exists between the channel and the body. Since the inversion layer of a MOSFET is electrically connected to the source, a voltage can be applied to the channel. V G ≥ V TH If the source/channel of an NMOS device is biased at a higher potential (V C ) than the body potential (V B ), the channel-to- body PN junction is reverse biased.  The potential drop across the depletion region is increased.  The depletion width is increased:  The depletion charge density (Q dep = qN A X d ) is increased.  The inversion-layer charge density is decreased, i.e. V TH is increased.

EE105 Fall 2007Lecture 16, Slide 4Prof. Liu, UC Berkeley Small-Signal Capacitance The MOS capacitor is a non-linear capacitor: If an incremental (small-signal) voltage dV G is applied in addition to a bias voltage V G, the total charge on the gate is Thus, the incremental gate charge (dQ G ) resulting from the incremental gate voltage (dV G ) is C G is the small-signal gate capacitance: constant charge

EE105 Fall 2007Lecture 16, Slide 5Prof. Liu, UC Berkeley (N)MOS C-V Curve The MOS C-V curve is obtained by taking the slope of the Q-V curve.  C G = C ox in the accumulation and inversion regions of operation.  C G is smaller, and is a non-linear function of V GB in the depletion region of operation.

EE105 Fall 2007Lecture 16, Slide 6Prof. Liu, UC Berkeley MOS Small-Signal Capacitance Model Accumulation Depletion Inversion The incremental charge is located at the semiconductor surface The incremental charge is located at the bottom edge of the depletion region The incremental charge is located at the semiconductor surface

EE105 Fall 2007Lecture 16, Slide 7Prof. Liu, UC Berkeley MOS Capacitive Voltage Divider In the depletion (sub-threshold) region of operation, an incremental change in the gate voltage (  V GB ) results in an incremental change in the channel potential (  V CB ) that is smaller than  V GB : How can we maximize  V CB /  V GB ?

EE105 Fall 2007Lecture 16, Slide 8Prof. Liu, UC Berkeley PMOS Capacitor Depletion V TH <V GB < V FB The PMOS structure can also be considered as a parallel-plate capacitor, but with the top plate being the negative plate, the gate insulator being the dielectric, and the n-type semiconductor substrate being the positive plate. – The positive charges in the semiconductor (for V GB < V FB ) are comprised of holes and/or donor ions. Accumulation V GB > V FB -t ox 0 XdXd 0 Inversion V GB < V TH -t ox X d,max 0

EE105 Fall 2007Lecture 16, Slide 9Prof. Liu, UC Berkeley PMOS Q-V, C-V inversion accumulation depletion inversionaccumulation depletion

EE105 Fall 2007Lecture 16, Slide 10Prof. Liu, UC Berkeley MOSFET in ON State (V GS > V TH ) The channel charge density is equal to the gate capacitance times the gate voltage in excess of the threshold voltage. Areal inversion charge density [C/cm 2 ]: Note that the reference voltage is the source voltage. In this case, V TH is defined as the value of V GS at which the channel surface is strongly inverted (i.e. n = N A at x=0, for an NMOSFET).

EE105 Fall 2007Lecture 16, Slide 11Prof. Liu, UC Berkeley Note that MOSFET as Voltage-Controlled Resistor For small V DS, the MOSFET can be viewed as a resistor, with the channel resistance depending on the gate voltage.

EE105 Fall 2007Lecture 16, Slide 12Prof. Liu, UC Berkeley MOSFET Channel Potential Variation If the drain is biased at a higher potential than the source, the channel potential increases from the source to the drain.  The potential difference between the gate and channel decreases from the source to drain.

EE105 Fall 2007Lecture 16, Slide 13Prof. Liu, UC Berkeley Charge Density along the Channel The channel potential varies with position along the channel: The current flowing in the channel is The carrier drift velocity at position y is where  n is the electron field-effect mobility

EE105 Fall 2007Lecture 16, Slide 14Prof. Liu, UC Berkeley Drain Current, I D (for V DS <V GS -V TH ) Integrating from source to drain:

EE105 Fall 2007Lecture 16, Slide 15Prof. Liu, UC Berkeley I D -V DS Characteristic For a fixed value of V GS, I D is a parabolic function of V DS. I D reaches a maximum value at V DS = V GS - V TH.

EE105 Fall 2007Lecture 16, Slide 16Prof. Liu, UC Berkeley Inversion-Layer Pinch-Off (V DS >V GS -V TH ) When V DS = V GS -V TH, Q inv = 0 at the drain end of the channel.  The channel is “pinched-off”. As V DS increases above V GS -V TH, the pinch-off point (where Q inv = 0) moves toward the source. – Note that the channel potential V C is always equal to V GS -V TH at the pinch-off point.  The maximum voltage that can be applied across the inversion-layer channel (from source to drain) is V GS -V TH.  The drain current “saturates” at a maximum value.

EE105 Fall 2007Lecture 16, Slide 17Prof. Liu, UC Berkeley Current Flow in Pinch-Off Region Under the influence of the lateral electric field, carriers drift from the source (through the inversion-layer channel) toward the drain. A large lateral electric field exists in the pinch-off region: Once carriers reach the pinch-off point, they are swept into the drain by the electric field.

EE105 Fall 2007Lecture 16, Slide 18Prof. Liu, UC Berkeley Drain Current Saturation (Long-Channel MOSFET) For V DS > V GS -V TH :

EE105 Fall 2007Lecture 16, Slide 19Prof. Liu, UC Berkeley MOSFET Regions of Operation When the potential difference between the gate and drain is equal to or less than V TH, the MOSFET is operating in the saturation region. When the potential difference between the gate and drain is greater than V TH, the MOSFET is operating in the triode region.

EE105 Fall 2007Lecture 16, Slide 20Prof. Liu, UC Berkeley Triode or Saturation? In DC circuit analysis, when the MOSFET region of operation is not known, an intelligent guess should be made; then the resulting answer should be checked against the assumption. Example: Given  n C ox = 100  A/V 2, V TH = 0.4V. If V G increases by 10mV, what is the change in V D ?