CSCI 660 CSCI-660 Introduction to VLSI Design Khurram Kazi

CSCI Course Outline  Overview of ASIC design flow  VHDL targeted for Synthesis  Synthesis  Constraining and Optimizing Design  Area and Timing reports  Verification  Self Checking Design Verification Concepts  Behavioral modeling for Test Benches in VHDL  SystemC  Verilog for Synthesis  Gate Level Verification

CSCI Recommended Books + useful links 1.HDL Programming Fundamentals; VHDL and Verilog, Nazeih, B. Botros, Da Vinci Engineering Press, 2006, ISBN: The Designer's Guide to VHDL (2nd edition), ISBN , Publisher: Morgan Kaufman, May Verilog HDL, Samir Palnitkar, 2nd Edition, SunSoft Press; A Prentice Hall Title, 2003, ISBN: Verification Methodology Manual for SystemVerilog (Hardcover), by Janick Bergeron, Eduard Cerny, Alan Hunter, Andy Nightingale, Springer; 1 edition (September 28, 2005), ISBN-10: Advanced ASIC Chip Synthesis: Using Synopsys® Design Compiler™ and PrimeTime®, Himanshu Bhatnagar, Kluwer Academic Publishers, 2nd Edition, ISBN: This webpage has tons of useful information!! Go over the ModelSim content as we will be using it as the simulator

CSCI Tools used in the course  Mentor Graphics ModelSim  VHDL simulator  Verilog simulator  System Verilog simulator  Synopsys  Synthesis tool  Static Timing Analysis  Remote access to our tools is available  Please send an to Mike Madigan for remote access account

CSCI Grading Policy  Homework/Short Quizzes 30%  1 Midterm Test30%  Final Project40%  Final Projects will be customized to your field of specialization, may it be in Data Networking, Cryptography, Specialized Arithmetic Operations, DSP, Computer Architecture etc.  Oral and written communication skills will be stressed in this course and taken into account for the final grade

CSCI Do’s and Don’ts for the Final Project  DO NOT use any off the shelf general purpose microprocessor or any other circuit taken from the publicly available information base. I will know if you did!!  Come up with your own functional idea and Implement it. Be creative ! Have a system’s perspective and see how your design fits in the system.  By mid semester have a good idea of your project  Team of 2 students working on the same project is allowed.  Each team member’s task within the project should be explicitly defined.

CSCI Teamwork Encouraged: How much collaboration is acceptable  Since time will be short, I would encourage you to help out your fellow students with the “Usage of the Tools” but not the Design. Informing me of the help received is strongly encouraged, i.e. give credit where credit is due!!  Helping fellow students with Tools usage and class participation will be rewarded in the final grade.

CSCI Where to Start in the ASIC Process! Begin with ASIC (Application Specific Integrated Circuit) Specification  Most likely by the time you are done with the design the Final Spec. will be quite different than the original ideas  Based on performance and functional requirements define operating frequencies, I/O pad types, operating conditions, verification and test requirements to ensure error free design and manufacturability of it

CSCI Implication of the Designs we work on; keep few things in mind!  During the design process we always make trade-offs  Trade-offs can be based on time to market, cost implications, complexity, environmental considerations etc.  Ethics: Keep in mind the implications of what you are designing, how it impacts the society!!  Digital designs inherently deal with  Implementing approximate solutions  Power consumption considerations: Making the Designs Green; Environmental friendly!!  Cost/performance trade-offs

CSCI Implication of the Designs we work on; keep few things in mind!  Few bad approximations lead to  Example: Failure of Patriot Missile (1991 Feb. 25)  Source  American Patriot Missile battery in Dharan, Saudi Arabia, failed to intercept incoming Iraqi Scud missile The Scud struck an American Army barracks, killing 28  Cause, per GAO/IMTEC report: “software problem” (inaccurate calculation of the time since boot)  Specifics of the problem: time in tenths of second as measured by the system’s internal clock was multiplied by 1/10 to get the time in seconds Internal registers were 24 bits wide 1/10 = (chopped to 24 b) ´ ´ 10 –8 Error in 100-hr operation 9.5 ´ 10 –8 ´ 100 ´ 60 ´ 60 ´ 10 = 0.34 s  Distance traveled by Scud = (0.34 s) ´ ( m, this put the Scud outside the Patriot’s “range gate”. Ironically, the fact that the bad time calculation had been improved in some (but not all) code parts contributed to the problem, since it meant that inaccuracies did not cancel out

CSCI Implication of the Designs we work on; keep few things in mind!  Few bad approximations lead to  Example: Explosion of Ariane Rocket (1996 June 4)  Source  Unmanned Ariane 5 rocket launched by the European Space Agency veered off its flight path, broke up, and exploded only 30 seconds after lift-off (altitude of 3700 m). The $500 million rocket (with cargo) was on its 1st voyage after a decade of development costing $7 billion  Cause: “software error in the inertial reference system”  Specifics of the problem: a 64 bit floating point number relating to the horizontal velocity of the rocket was being converted to a 16 bit signed integer  An SRI* software exception arose during conversion because the 64-bit floating point number had a value greater than what could be represented by a 16-bit signed integer (max )

CSCI Overview of some of the steps in an ASIC design flow RTL code implies synthesizable HDL code

CSCI RTL Block Synthesis* *Simplified design flow

CSCI Insert Test Structure (Internal Scan and JTAG)* *Simplified design flow Note that we will not cover JTAG or insertion of the boundary scan in this class

CSCI Insert Test Structure (Internal Scan and JTAG)* *Simplified design flow Note that we will not cover JTAG or insertion of the boundary scan in this class

CSCI Insert I/O Pads* *Simplified design flow

CSCI ASIC Floorplan* *Simplified design flow

CSCI Getting ASIC Ready for Handoff* *Simplified design flow

CSCI Brief History of VHDL  VHDL is a language used for designing and simulating digital hardware. It has been adopted by the electronics industry worldwide. Another Language that is also widely used is Verilog  VHDL is an acronym for V HSIC ( V ery H igh S peed I ntegrated C ircuit) H ardware D escription L anguage  VHDL originally was used for specifications  Subsequently was used for simulating designs  Finally its scope evolved into its usage for synthesizing digital designs

CSCI Levels of Abstraction Slide taken from K.Gaj lectures at GMU Algorithmic level Register Transfer Level Logic (gate) level Circuit (transistor) level Physical (layout) level Level of description most suitable for synthesis

CSCI Register Transfer Logic (RTL) Slide taken from K.Gaj lectures at GMU Combinational Logic Combinational Logic Registers

CSCI Levels at which VHDL can be used Slide taken from K.Gaj lectures at GMU VHDL for Simulation VHDL for Synthesis VHDL for Specification

CSCI Typical HDL Design Environment Testbench (Generator In C or HDL) Testbench (Analyzer In C or HDL) HDL Design (VHDL or Verilog Reference Model ( In C or Functional HDL) HDL (Hardware Description Language) can typically be either VHDL or Verilog

CSCI Overview of VHDL  Library and Library Declarations  Entity Declaration  Architecture  Configuration

CSCI Overview of VHDL  Package (typically compiled into the destination library) contains commonly used declarations  Constants maybe defined here  Enumerated data types (Red, Green, Blue)  Combinatorial functions (performing a decode function; returns single value)  Procedures (can return multiple values)  Component declarations

CSCI Overview of VHDL: Example of Library Declaration LIBRARY library_name;--comments USE library_name.package_name.package_parts;-- VHDL is case -- insesitive Typically there are three different libraries used in a design 1) ieee.std_logic_1164 (from the ieee library) 2) standard (from the std library) 3) work ( work library)  std_logic_1164 : Specifies the STD_LOGIC (8 levels) and the STD_ULOGIC (9 levels) multi-values logic systems  std : It is a resource library (data types, text i/o, etc.)  work : This is where the design is saved Library ieee;-- A semi-colon (;) indicates the end of a statement or a declaration USE ieee.std_logic_1164.all;-- double dash indicates a comment. Library std; USE std.standard.all; Library work; USE work.all;

CSCI Overview of VHDL: Entity  Entity  Defines the component name, its inputs and outputs (I/Os) and related declarations.  Can use same Entity for different architecture to study various design trade offs.  Use std_logic and std_logic_vector(n downto 0) : they are synthesis friendly.  Avoid enumerated type of I/Os.  Avoid using port type buffer or bidir (unless you have to)

CSCI Overview of VHDL: Syntax of an Entity 1.ENTITY entity_name IS PORT ( port_name: signal_modesignal type; ……….); END entity_name; 2.ENTITY nand_gate IS PORT ( a:INstd_logic; b:INstd_logic; x:OUTstd_logic); END nand_gate; or 3.ENTITY FiveInput_nand_gate IS PORT ( a:INstd_logic_vector (4 downto 0); x:OUTstd_logic); END FiveInput_nand_gate;

CSCI Overview of VHDL: Architecture  Architecture  Defines the functionality of the design  Normally consists of processes and concurrent signal assignments  Synchronous and/or combinatorial logic can be inferred from the way functionality is defined in the Processes.  Avoid nested loops  Avoid generate statements with large indices  Always think hardware when developing code!  One way of looking at is how would you implement the digital design on the breadboard; mimic the same thought process in writing VHDL code

CSCI Overview of VHDL: Syntax of an Architecture ARCHITECTURE architecture_name OF entity_name IS [declarations] BEGIN (code) END architecture_name; ARCHITECTURE myarch OF nand_gate IS BEGIN x <= a NAND b; END myarch;

CSCI Overview of VHDL: Basic Components of an Architecture  Primarily Architecture consists of  Process  Concurrent Statements  Code in VHDL is inherently concurrent (parallel)  All processes and concurrent statements are evaluated in parallel (i.e. at the same time)  Code inside the process is executed sequentially  The code execution is based on sensitivity list (signals that act as triggers in the execution of the respective process  Process can describe  Asynchronous (combinatorial logic)  Synchronous (clocked logic)  Concurrent Statements  Typically combinatorial logic is implemented using concurrent statements

CSCI Separation of Combinatorial and Sequential Logic Signals within the sensitivity list

CSCI Case statement Synthesis

CSCI Synthesis of “if – then – elsif” statement

CSCI Overview of VHDL  Configuration  Primarily used during the simulations  If there are multiple architectures for the same entity, the “configuration” can be used to instruct the simulator which architecture should be used during the simulation.

CSCI Some useful practices  Organize Your Design Workspace  Define naming convention (especially if multiple designers are on the project  Completely Specify Sensitivity Lists  Try to separate combinatorial logic from sequential logic