ELEN 468 Lecture 221 ELEN 468 Advanced Logic Design Lecture 22 Timing Verification.

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Presentation transcript:

ELEN 468 Lecture 221 ELEN 468 Advanced Logic Design Lecture 22 Timing Verification

ELEN 468 Lecture 222 General Timing verifications should be performed at every design stage Timing verifications at early stages are not accurate as no detailed physical information available

ELEN 468 Lecture 223 Type of Timing Paths 1. Input -> register 2. Register -> register 3. Register -> output 4. Input -> output Combinational Logic Register Combinational Logic Register Clock

ELEN 468 Lecture 224 Clock Scheduling Register Combinational Logic Register Clock ij titi tjtj LD: logic delay

ELEN 468 Lecture 225 Timing Constraints skew ij = t i – t j <= CP – LD max – setup max (long path) skew ij = t i – t j >= hold max – LD min (short path) tjtj titi holdsetup LD min LD max CP

ELEN 468 Lecture 226 Static Timing Analysis Arrival time: input -> output, take max Required arrival time: output -> input, take min Slack = required arrival time – arrival time /4/-3 5/3/-2 4/7/34/7/3 8/8/08/8/0 9/6/-3 20/17/-3 11/11/0 18/18/0 23/20/-3

ELEN 468 Lecture 227 False Paths [3:5, 2:3] Min, max risingMin, max falling Max path delay = 15?

ELEN 468 Lecture 228 Dynamically Sensitized Paths a b c d ‘0’ a b c d

ELEN 468 Lecture 229 Gate and Wire Model CR LrL cL/2 r: resistance per unit length c: capacitance per unit length

ELEN 468 Lecture 2210 Example of Model L1L1 L2L2 L3L3 C2C2 C3C RrL 1 rL 2 rL 3 cL 1 /2 (L 1 +L 2 +L 3 )c/2 cL 2 /2+C 2 cL 3 /2+C 3

ELEN 468 Lecture 2211 Delay Estimation D 0 = R ( C 0 + C 1 + C 2 + C 3 ) D 1 = D 0 + R 1 ( C 1 + C 2 + C 3 ) D 2 = D 1 + R 2 C 2 D 3 = D 1 + R 3 C RR1R1 R2R2 R3R3 C0C0 C2C2 C3C3 C1C1

ELEN 468 Lecture 2212 Interconnect Size Scaling Wire width scales faster than wire height  wires are thinner and taller Wires are placed closer Coupling capacitance start to dominate substrate capacitance

ELEN 468 Lecture 2213 Crosstalk Noise Crosstalk noise may cause Glitch and logical error Extra propagation delay aggressor victim

ELEN 468 Lecture 2214 Elimination of Timing Violation ActionEffect Increase clock periodEliminates the violation, constrained by specifications Reroute critical pathReduce interconnect delays Resize and substitute devicesReduce device delays and improve setup and hold margins Redesign clock treeReduce clock skew Substitute a different algorithmReduce path delays Substitute architectureReduce path delays Pipeline/retimingReduce path delays Change technologiesReduce path and device delays