Computer Engineering (Logic Circuits) (Karnaugh Map)

Slides:



Advertisements
Similar presentations
Gate-Level Minimization
Advertisements

Boolean Algebra and Reduction Techniques
K-Map Simplification COE 202 Digital Logic Design Dr. Aiman El-Maleh
Based on slides by: Charles Kime & Thomas Kaminski © 2004 Pearson Education, Inc. ECE/CS 352: Digital System Fundamentals Lecture 8 – Systematic Simplification.
Gate-level Minimization
Gate-Level Minimization. Digital Circuits The Map Method The complexity of the digital logic gates the complexity of the algebraic expression.
Chapter 3 Simplification of Switching Functions
Circuit Optimization Goal: To obtain the simplest implementation for a given function Optimization is a more formal approach to simplification that is.
Give qualifications of instructors: DAP

EET 1131 Unit 5 Boolean Algebra and Reduction Techniques
Introduction Gate-level minimization refers to the design task of finding an optimal gate-level implementation of Boolean functions describing a digital.
بهينه سازي با نقشة کارنو Karnaugh Map. 2  Method of graphically representing the truth table that helps visualize adjacencies 2-variable K-map 3-variable.
EECC341 - Shaaban #1 Lec # 7 Winter Combinational Circuit Minimization Canonical sum and product logic expressions do not provide a circuit.
Simplifying Boolean Expressions Using K-Map Method
Overview Part 2 – Circuit Optimization 2-4 Two-Level Optimization
Overview of Chapter 3 °K-maps: an alternate approach to representing Boolean functions °K-map representation can be used to minimize Boolean functions.
BOOLEAN ALGEBRA Saras M. Srivastava PGT (Computer Science)
1 Simplification of Boolean Functions:  An implementation of a Boolean Function requires the use of logic gates.  A smaller number of gates, with each.
CT455: Computer Organization K-Map
1 Chapter 5 Karnaugh Maps Mei Yang ECG Logic Design 1.
Chapter 3 Simplification of Switching Functions. Simplification Goals Goal -- minimize the cost of realizing a switching function Cost measures and other.
Department of Computer Engineering
1 Digital Logic Design Week 5 Simplifying logic expressions.
D IGITAL L OGIC D ESIGN I G ATE -L EVEL M INIMIZATION.
Optimization Algorithm
Charles Kime & Thomas Kaminski © 2008 Pearson Education, Inc. Circuit Optimization Logic and Computer Design Fundamentals.
Chapter 3 Gate-Level Minimization
ECE 2110: Introduction to Digital Systems PoS minimization Don’t care conditions.
Examples. Examples (1/11)  Example #1: f(A,B,C,D) =  m(2,3,4,5,7,8,10,13,15) Fill in the 1’s. 1 1 C A B CD AB D 1 1.
ECE 3110: Introduction to Digital Systems Symplifying Products of sums using Karnaugh Maps.
Combinational Logic Part 2: Karnaugh maps (quick).
Charles Kime & Thomas Kaminski © 2008 Pearson Education, Inc. (Hyperlinks are active in View Show mode) Chapter 2 – Combinational Logic Circuits Part 2.
PRASAD A. PAWASKAR SPN. NO DETE 2 SEMESTER lec1-11.
EE345 – Micro-Controllers Gate-Level Minimization Prof. Ahmad Abu-El-Haija.
Charles Kime & Thomas Kaminski © 2008 Pearson Education, Inc. (Hyperlinks are active in View Show mode) Chapter 2 – Combinational Logic Circuits Part 2.
Gate-Level Minimization
Gate-level Minimization
Computer Engineering (Logic Circuits) (Karnaugh Map)
Chapter3: Gate-Level Minimization Part 1 Origionally By Reham S. Al-Majed Imam Muhammad Bin Saud University.
07 KM Page 1 ECEn/CS 224 Karnaugh Maps. 07 KM Page 2 ECEn/CS 224 What are Karnaugh Maps? A simpler way to handle most (but not all) jobs of manipulating.
CHAPTER 3: PRINCIPLES OF COMBINATIONAL LOGIC
Lecture 4 Nand, Nor Gates, CS147 Circuit Minimization and
LOGIC GATES & BOOLEAN ALGEBRA
Ahmad Almulhem, KFUPM 2010 COE 202: Digital Logic Design Combinational Logic Part 3 Dr. Ahmad Almulhem ahmadsm AT kfupm Phone: Office:
Karnaugh Maps (K-Maps)
LOGIC CIRCUITLOGIC CIRCUIT. Goal To understand how digital a computer can work, at the lowest level. To understand what is possible and the limitations.
Boolean Algebra and Reduction Techniques
Karnaugh Mapping Digital Electronics. Karnaugh Mapping or K-Mapping This presentation will demonstrate how to Create and label two, three, & four variable.
Boolean Algebra & Logic Circuits Dr. Ahmed El-Bialy Dr. Sahar Fawzy.
Karnaugh Maps (K maps). What are Karnaugh 1 maps?  Karnaugh maps provide an alternative way of simplifying logic circuits.  Instead of using Boolean.
June 12, 2002© Howard Huang1 Karnaugh maps Last time we saw applications of Boolean logic to circuit design. – The basic Boolean operations are.
CHAPTER 1 INTRODUCTION TO DIGITAL LOGIC
1 Example: Groupings on 3-Variable K-Maps BC F(A,B,C) = A ’ B ’ A BC F(A,B,C) = B ’ A
Karnaugh Map (K-Map) By Dr. M. Khamis Mrs. Dua’a Al Sinari.
Digital Logic (Karnaugh Map). Karnaugh Maps Karnaugh maps (K-maps) are graphical representations of boolean functions. One map cell corresponds to a row.
CMPUT Computer Organization and Architecture II1 CMPUT329 - Fall 2003 Topic 4: Cost of Logic Circuits and Karnaugh Maps José Nelson Amaral.
Karnaugh Maps (K maps).
Chapter 3 Simplification of Switching Functions. Simplification Goals Goal -- minimize the cost of realizing a switching function Cost measures and other.
Mu.com.lec 9. Overview Gates, latches, memories and other logic components are used to design computer systems and their subsystems Good understanding.
CHAPTER 3 Simplification of Boolean Functions
Lecture 4 Nand, Nor Gates, CS147 Circuit Minimization and
Computer Organisation
CS 352 Introduction to Logic Design
CHAPTER 5 KARNAUGH MAPS 5.1 Minimum Forms of Switching Functions
CH7 Multilevel Gate Network
Karnaugh Maps Introduction Venn Diagrams 2-variable K-maps
Chapter 3 Gate-level Minimization.
COE 202: Digital Logic Design Combinational Logic Part 3
Overview Part 2 – Circuit Optimization
Presentation transcript:

Computer Engineering (Logic Circuits) (Karnaugh Map) Lec. # 5 (Karnaugh Map) Dr. Tamer Samy Gaafar Dept. of Computer & Systems Engineering Faculty of Engineering Zagazig University

Course Web Page http://www.tsgaafar.faculty.zu.edu.eg Email: tsgaafar@yahoo.com

Lec. # 5 Karnaugh Map

F = X’Y’Z + XY’Z’ + XY’Z + XYZ’ + XYZ SOP Functions Take 1’s from Truth Table Truth Table 1 1 1 1 1 1 0 1 0 1 1 0 0 0 1 1 0 1 0 0 0 1 0 0 0 X Y Z F F = X’Y’Z + XY’Z’ + XY’Z + XYZ’ + XYZ Simplify F = x + y’z

F’= x’y’z’ + x’yz’ + x’yz F = (x+y+z).(x+y’+z).(x+y’+z’) POS Functions Take 0’s from truth table (F’) Apply Demorgan (F) Truth Table 1 1 1 1 1 1 0 1 0 1 1 0 0 0 1 1 0 1 0 0 0 1 0 0 0 X Y Z F F’= x’y’z’ + x’yz’ + x’yz F = (x+y+z).(x+y’+z).(x+y’+z’)

Universal Gates: NAND and NOR AND/OR/NOT gates are sufficient for building any Boolean functions. We call the set {AND, OR, NOT} a complete set of logic.

(x.x)' = x' (T1: idempotency) NAND Gate (1/2) NAND gate is self-sufficient (can build any logic circuit with it). Therefore, {NAND} is also a complete set of logic. Can be used to implement AND/OR/NOT. Implementing an inverter using NAND gate: x x' (x.x)' = x' (T1: idempotency)

(x.y)= ((x.y)')' idempotency NAND Gate (2/2) Implementing AND using NAND gates: x x.y y (x.y)' (x.y)= ((x.y)')' idempotency = (xy) involution Implementing OR using NAND gates: x x+y y x' y' X+Y = (X+Y)’’ = ( X‘ . Y’) ‘

(x+x)' = x' (T1: idempotency) NOR Gate (1/2) NOR gate is also self-sufficient. Therefore, {NOR} is also a complete set of logic Can be used to implement AND/OR/NOT. Implementing an inverter using NOR gate: x x' (x+x)' = x' (T1: idempotency)

NOR Gate (2/2) Implementing AND using NOR gates: (XY) = (XY)’’ Implementing OR using NOR gates: x x+y y (x+y)' x+y = ((x+y)')‘ = (x+y)

Outline Universal Gates : NAND and NOR NAND Gate NOR Gate Implementation using NAND Gates Implementation using NOR Gates

Implementation using NAND gates (1/2) Possible to implement any Boolean expression using NAND gates. Procedure: (i) Obtain sum-of-products Boolean expression: Example: F3 = x.y'+x'.z (ii) Use DeMorgan theorem to obtain expression using 2-level NAND gates = (x.y'+x'.z)' ' involution = ((x.y')' . (x'.z)')' DeMorgan

Implementation using NAND gates (2/2) x' z F3 (x'.z)' (x.y')' x y' F3 = ((x.y')'.(x'.z)') ' = x.y' + x'.z NAND gate is used to implement a SOP Function

Outline Universal Gates : NAND and NOR NAND Gate NOR Gate Implementation using NAND Gates Implementation using NOR Gates

Implementation using NOR gates (1/2) Possible to implement any Boolean expression using NOR gates. Procedure: (i) Obtain product-of-sums Boolean expression: Example: F6 = (x+y').(x'+z) (ii) Use DeMorgan theorem to obtain expression using 2-level NOR gates. = ((x+y').(x'+z))' ' involution = ((x+y')'+(x'+z)')' DeMorgan

Implementation using NOR gates (2/2) x' z F6 (x'+z)' (x+y')' x y' F6 = ((x+y')'+(x'+z)')' = (x+y').(x'+z) NOR gate is used to implement a POS Function

Implementing a SOP using NOR gates Procedure: (i) Obtain sum-of-products Boolean expression: Example: F3 = x.y'+x'.z (ii) Take the Complement for both sides G = F3’= (x.y’+x’.z)’ Then G = F3’ = (x’+y) . (x+z’) Note: G = F3’ ----------- > POS ( NOR Implemention) but needs an Inverter

Implementation using NOR gates (2/2) X Z’ (x+z’)' (x’+y)' X’ Y G = F3’ F3 G = F3’ = (x’+y) . (x+z’) G’’ = [(x’+y)’ + (x+z’)’]’ NOR gate is used to implement a POS Function

Implementing POS using NAND gates Possible to implement any Boolean expression using NAND gates. Procedure: (i) Obtain product-of-sums Boolean expression: Example: F7 = (x+y').(x'+z) (ii) Use DeMorgan theorem to obtain expression using 2-level to represent as SOP F7’= x’.y+x.z’ DeMorgan

Implementation using NAND gates (2/2) X’ Z’ F7’ (X.Z’)' (X’.Y)' Y F7 F7’ = ((x’.y)'.(x.z’)') ' = x.y' + x.z’ NAND gate is used to implement a POS Function

Exclusive-OR (XOR) Exclusive-OR (XOR) produces a HIGH output whenever the two inputs are at opposite levels.

Exclusive-NOR Circuits (XNOR) Exclusive-NOR (XNOR) produces a HIGH output whenever the two inputs are at the same level.

XOR function can also be implemented with AND/OR gates (also NANDs).

Positive and Negative Logic Positive logic AND Negative Logic AND F B A 1 F B A 1

Karnaugh Maps (K maps)

What are Karnaugh maps? Karnaugh maps provide an alternative way of simplifying logic circuits. Instead of using Boolean algebra simplification techniques, you can transfer logic values from a Boolean statement or a truth table into a Karnaugh map. The arrangement of 0's and 1's within the map helps you to visualize the logic relationships between the variables and leads directly to a simplified Boolean statement.

Karnaugh maps A A A A B B B B 00 10 01 11 Karnaugh maps, or K-maps, are often used to simplify logic problems with 2, 3 or 4 variables. Cell = 2n ,where n is a number of variables For the case of 2 variables, we form a map consisting of 22=4 cells as shown in Figure A A A A A A 1 1 B B 00 10 01 11 B B 2 B 1 B 1 1 3 Minterm

Karnaugh maps A A C C B B B 3 variables Karnaugh map Cell = 23=8 AB C 00 01 11 10 2 6 4 C 1 3 7 5 C 1 B B B

Karnaugh maps A A C D D C D B B B 4 variables Karnaugh map AB 00 01 11 10 CD 4 12 8 C 00 D 1 5 13 9 01 D 3 7 15 11 11 C 2 6 14 10 10 D B B B

Cell numbers are written in the cells. 2-variable K-map Examples of K-Maps: Examples: Cell numbers are written in the cells. 2-variable K-map B B B 1 A A 1 2 3 A 1

3-Variable K-Map: 3-variable K-map B B 00 01 11 10 00 01 11 10 A 1 1 3 BC 00 01 11 10 00 01 11 10 BC A A A 1 1 3 2 4 5 7 6 1 A C C C

4-variable K-map CD AB 00 01 11 10 00 1 3 2 4 5 7 6 12 13 15 14 8 9 11 10 01 11 10

Four-variable K-maps

Karnaugh maps The Karnaugh map is completed by entering a ‘1’ (or ‘0’) in each of the appropriate cells. Within the map, adjacent cells containing 1's (or 0’s) are grouped together in twos, fours, or eights.

Karnaugh Mapping K-Map Format Digital Electronics 2.2 Intro to NAND & NOR Logic Each minterm in a truth table corresponds to a cell in the K- Map. K-Map cells are labeled such that both horizontal and vertical movement differ only by one variable. Since the adjacent cells differ by only one variable, they can be grouped to create simpler terms in the sum-of-products expression. The sum-of-products expression for the logic function can be obtained by OR-ing together the cells or group of cells that contain 1s. Explain how a K-Map is formatted and how a simplified logic expression can be written from the cell groupings. Project Lead The Way, Inc. Copyright 2009

Simplification Guidelines for K-maps Each cell of an n-variable K-map has n logically adjacent cells. Cells may be combined in groups of 2,4,8,…,2k. A group of cells can be combined only if all cells in the group have the same value for some set of variables. Always combine as many cells in a group as possible. This will result in the fewest number of literals in the term that represents the group. Make as few groupings as possible to cover all minterms. This will result in the fewest product terms. Always begin with the “loneliest” cells.

Minimization with K-maps Draw a K-map Combine maximum number of 1’s following rules: Only adjacent squares can be combined All 1’s must be covered Covering rectangles must be of size 1,2,4,8, … 2n Check if all covering are really needed Read off the SOP expression

2 variable K-Maps (Adjacency) In an n-variable k-map, each square is adjacent to exactly n other squares Q: What if you have 1 in all squares? Ahmad Almulhem, KFUPM 2009

Adjacent Cells = Simplification Karnaugh Mapping Adjacent Cells = Simplification Digital Electronics 2.2 Intro to NAND & NOR Logic V 1 V V 1 Adjacent cells only vary by one variable change. Review the proof that the one variable changing results in it being eliminated algebraically. This is fundamental to how a K-Map works. Project Lead The Way, Inc. Copyright 2009

Truth Table to K-Map Mapping Karnaugh Mapping Truth Table to K-Map Mapping Digital Electronics 2.2 Intro to NAND & NOR Logic Two Variable K-Map V 1 2 3 V W X FWX Minterm – 0 1 Minterm – 1 Minterm – 2 Minterm – 3 1 1 Demonstrate how the minterms of a two variable truth table are mapped to a K-Map. Project Lead The Way, Inc. Copyright 2009

Two Variable K-Map Groupings Karnaugh Mapping Digital Electronics 2.2 Intro to NAND & NOR Logic Two Variable K-Map Groupings Groups of One – 4 V 1 1 1 1 Two variable K-Map, groups of one. Project Lead The Way, Inc. Copyright 2009

Two Variable K-Map Groupings Karnaugh Mapping Digital Electronics 2.2 Intro to NAND & NOR Logic Two Variable K-Map Groupings Groups of Two – 4 V 1 1 1 1 Two variable K-Map, groups of two. Project Lead The Way, Inc. Copyright 2009

Two Variable K-Map Groupings Karnaugh Mapping Digital Electronics 2.2 Intro to NAND & NOR Logic Two Variable K-Map Groupings Group of Four – 1 V 1 Two variable K-Map, group of four. Project Lead The Way, Inc. Copyright 2009

Example #1: 2 Variable K-Map Karnaugh Mapping Example #1: 2 Variable K-Map Digital Electronics 2.2 Intro to NAND & NOR Logic Example: After labeling and transferring the truth table data into the K-Map, write the simplified sum-of-products (SOP) logic expression for the logic function F1. V J K F1 1 Pause the presentation and allow the student to complete the example. The solution is on the next slide. Project Lead The Way, Inc. Copyright 2009

Example #1: 2 Variable K-Map Karnaugh Mapping Example #1: 2 Variable K-Map Digital Electronics 2.2 Intro to NAND & NOR Logic Example: After labeling and transferring the truth table data into the K-Map, write the simplified sum-of-products (SOP) logic expression for the logic function F1. Solution: V 1 J K F1 1 Here is the solution. If you print handouts, do not print this page. Project Lead The Way, Inc. Copyright 2009

Truth Table to K-Map Mapping Three Variable K-Map

3-variable K-maps For 3-variable functions, the k-maps are larger and look different. Total number of minterms that need to be accommodated in the k-map = 8 To maintain adjacency neighbors don’t have more than 1 different bit B BC A 00 01 11 10 1 m0 m1 m3 m2 m4 m5 m7 m6 A C

3-variable K-maps BC A 00 01 11 10 1 m0 m1 m3 m2 m4 m5 m7 m6 00 01 11 10 1 m0 m1 m3 m2 m4 m5 m7 m6 Note: You can only combine a power of 2 adjacent 1-squares. For e.g. 2, 4, 8, 16 squares. You cannot combine 3, 7 or 5 squares BC A 00 01 11 10 1 m0 m1 m3 m2 m4 m5 m7 m6 Minterms mo, m2, m4, m6 can be combined as m0 and m2 are adjacent to each other, m4 and m6 are adjacent to each other mo and m4 are also adjacent to each other, m2 and m6 are also adjacent to each other

Example 1 Simplify F = ∑m(1, 3, 4, 6) using K-map B BC A 00 01 11 10 1 1 3 2 4 5 7 6 A C

Example 1 F = A’C + AC’ Simplify F = ∑m(1, 3, 4, 6) using K-map B BC A 00 01 11 10 1 3 2 4 5 7 6 F = A’C + AC’ A C

Example 2 Simplify F = ∑m(0,1, 2, 4, 6) using K-map B B A 00 01 11 10 1 3 2 4 5 7 6 A C

Example 2 F = A’ B’ + C’ Simplify F = ∑m(0,1, 2, 4, 6) using K-map B B 00 01 11 10 1 3 2 4 5 7 6 F = A’ B’ + C’ A C

3 variable K-Maps (Adjacency) A 3-variable map has 12 possible groups of 2 minterms They become product terms with 2 literals 00 01 11 10 1 00 01 11 10 1 00 01 11 10 1

3 variable K-Maps (Adjacency) A 3-variable map has 6 possible groups of 4 minterms They become product terms with 1 literals 00 01 11 10 1 00 01 11 10 1 00 01 11 10 1

Example F = CD + A’D + BC + AB’C’ Minimize the function F(A,B,C,D)=∑m(1,3,5,6,7,8,9,11,14,15) C CD AB 00 01 11 10 00 01 11 10 1 1 1 1 1 B 1 1 A 1 1 1 D F = CD + A’D + BC + AB’C’

Example F(A,B,C,D) = Sm(0,1,2,5,8,9,10) CD AB 00 01 11 10 1 C=1 B=1

Example F(A,B,C,D) =Sm(0,1,2,5,8,9,10) F = B’ D’ + B’ C’ + A’ C’ D Solution: F = B’ D’ + B’ C’ + A’ C’ D CD AB 00 01 11 10 1 C=1 B=1 A=1 D=1

Example (POS) F(A,B,C,D) = Sm(0,1,2,5,8,9,10) Write F in the simplified product of sums (POS) Two methods? You already know one! CD AB 00 01 11 10 1 C=1 B=1 A=1 D=1

Example (POS) F’’ = F = (A’+B’)(C’+D’)(B’+D) F(A,B,C,D) = Sm(0,1,2,5,8,9,10) Write F in the simplified product of sums (POS) Follow same rule as before but for the ZEROs F’ = AB + CD + BD’ Therefore, F’’ = F = (A’+B’)(C’+D’)(B’+D) CD AB 00 01 11 10 1 C=1 B=1 A=1 D=1

Truth Table to K-Map Mapping Karnaugh Mapping Truth Table to K-Map Mapping Digital Electronics 2.2 Intro to NAND & NOR Logic Four Variable K-Map W X Y Z FWXYZ Minterm – 0 Minterm – 1 1 Minterm – 2 Minterm – 3 Minterm – 4 Minterm – 5 Minterm – 6 Minterm – 7 Minterm – 8 Minterm – 9 Minterm – 10 Minterm – 11 Minterm – 12 Minterm – 13 Minterm – 14 Minterm – 15 1 V 1 3 2 4 5 7 6 12 13 15 14 8 9 11 10 1 1 1 Demonstrate how the minterms of a four variable truth table are mapped to a K-Map. Project Lead The Way, Inc. Copyright 2009

Four Variable K-Map Groupings Karnaugh Mapping Digital Electronics 2.2 Intro to NAND & NOR Logic Four Variable K-Map Groupings Groups of One – 16 (not shown) Groups of Two – 32 (not shown) Groups of Four – 24 (seven shown) 1 1 1 V 1 1 1 1 Four Variable K-Map: There are 16 groups of one that are not shown because they are obvious. There are 32 groups of two that are not shown because they are obvious. There are 24 groups of four. Seven are show, the other 17 are obvious. Project Lead The Way, Inc. Copyright 2009

Four Variable K-Map Groupings Karnaugh Mapping Digital Electronics 2.2 Intro to NAND & NOR Logic Four Variable K-Map Groupings Groups of Eight – 8 (two shown) 1 V 1 Four variable K-Map: There are 8 groups of eight. Two are shown, the other 6 are obvious. Project Lead The Way, Inc. Copyright 2009

Four Variable K-Map Groupings Karnaugh Mapping Digital Electronics 2.2 Intro to NAND & NOR Logic Four Variable K-Map Groupings Group of Sixteen – 1 V 1 Four variable K-Map, group of 16. Project Lead The Way, Inc. Copyright 2009

Example : 4 Variable K-Map Karnaugh Mapping Example : 4 Variable K-Map Digital Electronics 2.2 Intro to NAND & NOR Logic Example: After labeling and transferring the truth table data into the K-Map, write the simplified sum-of-products (SOP) logic expression for the logic function F3. R S T U F3 1 V Pause the presentation and allow students to complete the example. The solution is on the next slide. Project Lead The Way, Inc. Copyright 2009

Example : 4 Variable K-Map Karnaugh Mapping Digital Electronics 2.2 Intro to NAND & NOR Logic Example: After labeling and transferring the truth-table data into the K-Map, write the simplified sum-of-products (SOP) logic expression for the logic function F3. R S T U F3 1 V 1 Solution: Here is the solution. If you print handouts, do not print this page. Project Lead The Way, Inc. Copyright 2009

Steps of graphical method (continued): Combine adjacent 1’s into group of 2n each such that Each group contains only 1’s. The group is not completely a part of a larger group. Choose the minimum number of the largest sized groups needed to cover all the 1’s. Each group is represented by an expression which is an intersection of the minterm in the group. The simplified solution is a logical OR of the expressions of all the groups chosen in steps 3 above.

Definitions An implicant is a product term of a function Any group of 1’s in a K-Map A prime implicant is a product term obtained by combining the maximum possible number of adjacent 1’s in a k-map Biggest groups of 1’s Not all prime implicants are needed! If a minterm is covered by exactly one prime implicant then this prime implicant is called an essential prime implicant

Example Y=1 Consider F(X,Y,Z) = Sm(1,3,4,5,6) List all implicants, prime implicants and essential prime implicants Solution: Implicants: XY’Z’, XZ’, XY’, XY’Z, X’Y’Z, Y’Z, … P.Is: XY’, XZ’, Y’Z, X’Z EPIs: X’Z, XZ’ YZ X 00 01 11 10 1 X=1 Z=1 Y=1 YZ X 00 01 11 10 1 X=1 The simplest expression is NOT unique! Z=1

Finding minimum SOP Find each essential prime implicant and include it in the solution If any minterms are not yet covered, find minimum number of prime implicants to cover them (minimize overlap).

Example Simplify F(A, B, C, D) = ∑ m(0, 1, 2, 4, 5, 10,11,13, 15) Note: Only A’C’ is E.P.I For the remaining minterms: Choose 1 and 2 (minimize overlap) For m2, choose either A’B’D’ or B’CD’ F = A’C’ + ABD + AB’C + A’B’D’

Examples to illustrate terms 0 0 1 1 1 0 D A 0 1 B C 5 prime implicants: BD, ABC', ACD, A'BC, A'C'D essential minimum cover: 4 essential implicants

4 Variable Maps f(A,B,C,D) = m(0,1,2,3,6,8,9,11,13,14) f = A C' D + B C D' + B' C ' + B' D + A'B' C D A B 00 01 11 10 1

These are not essential! Another 4 Variable Map f(A,B,C,D) = m(0,1,2,5,6,7,8,9,10,13,15) f = B D + A' B C + B' D' + B' C' or f = B D + A' B C + B' D' + C' D (there are 2 more) C D A B 00 01 11 10 1 These are not essential!

Terminology An implicant is a product term in an SOP expression (or a sum term in POS expression) Implicants are always rectangular in shape and the # of 1's covered is a power of 2 A prime implicant is an implicant that is not fully contained in some other larger implicant B C A 00 01 11 10 1 red  implicant (but not prime) many more are not shown blue  prime implicants (only two)

Essential Prime Implicants An essential prime implicant is a prime implicant that contains a 1 not included in any other prime implicant The minimum Boolean expression must use this term A cover is a collection of implicants that accounts for all valuations in which the function is “on” (e.g. 1)

essential prime implicants Find the Essential Prime Implicants C D A B 00 01 11 10 1 C D A B 00 01 11 10 1 essential prime implicants f = C'D' + A'B + B'D' + ACD

1 square = a term with 4 literals 2 square = a term with 3 literal 16 square = a function equal to 1 Y YZ 0 0 0 1 1 1 10 WX 00 01 X 11 W 10 Z

Simplification of kmap Generate all PIs Find EPIs If EPIs can cover all minterms, then it is answer. Otherwise choose some non-essential PIs (which has less cost) such that all minterms are cover.

Step 1 Generate PIs Blue circle are PIs They are the largest circle you can drawn on kmap

Step 2 Find EPIs Red circle are EPIs Minterm 5, 14, 11 can only be cover by these 3 red circle

Step 3 EPIs cannot cover minterm 7 Choose between green/blue circle to cover minterm 7 Green is chosen as it is larger Less cost

Final Final result is obtained x3x4’ + x2’x3 + x1’x3 + x2x3’x4