1. Overview of Chapter 3 °K-maps: an alternate approach to representing Boolean functions °K-map representation can be used to minimize Boolean functions °Easy conversion from truth table to K-map to minimized SOP representation. °Simple rules (steps) used to perform minimization °Leads to minimized SOP representation. Much faster and more more efficient than previous minimization techniques with Boolean algebra.

2. xyF001011100110xyF001011100110 Karnaugh maps °Alternate way of representing Boolean function All rows of truth table represented with a square Each square represents a minterm °Easy to convert between truth table, K-map, and SOP Unoptimized form: number of 1’s in K-map equals number of minterms (products) in SOP Optimized form: reduced number of minterms 01 y x 0 1 1 00 1 01 y x 0 1 x’y’ xy’xy x’y x y F = Σ(m 0,m 1 ) = x’y + x’y’

3. Karnaugh Maps °A Karnaugh map is a graphical tool for assisting in the general simplification procedure. °Two variable maps. 0 A 10 1 B 01 0 1 F=AB +A ’ B 0 A 11 1 B 01 0 1 °Three variable maps. 0 A 11 1 0001 0 1 BC 0 11 1 1110 F=AB’C’ +A B C + ABC +A BC + A’B’C + A’BC’ F=AB + AB + AB AB C F 0000 0011 0101 0110 1001 1011 1101 1111 +

4. Rules for K-Maps  We can reduce functions by circling 1’s in the K-map  Each circle represents minterm reduction  Following circling, we can deduce minimized and-or form. Rules to consider Ê Every cell containing a 1 must be included at least once. Ë The largest possible “power of 2 rectangle” must be enclosed. Ì The 1’s must be enclosed in the smallest possible number of rectangles. Example

5. Karnaugh Maps °A Karnaugh map is a graphical tool for assisting in the general simplification procedure. °Two variable maps. 0 A 10 1 B 01 0 1 F=AB +A ’ B 0 A 11 1 B 01 0 1 F=A + B °Three variable maps. F=A + B C + BC 0 A 11 1 0001 0 1 BC 0 11 1 1110 F=AB + AB + AB F=AB’C’ +A B C + ABC +A BC + A’B’C + A’BC’

6. Karnaugh maps °Numbering scheme based on Gray–code e.g., 00, 01, 11, 10 Only a single bit changes in code for adjacent map cells This is necessary to observe the variable transitions 0001 AB C 0 1 1110 C B A F(A,B,C) =  m(0,4,5,7) G(A,B,C) = 0011 C B A 100010000 011101111 C B A A = AC + B’C’

7. More Karnaugh Map Examples °Examples g = b' 01 0 1 a b c ab 00011110 0 1 01 0 1 a b c ab 00011110 0 1 01 01 f = a 0010 0111 cout = ab + bc + ac 11 00 0011 0011 f = a 1. Circle the largest groups possible. 2. Group dimensions must be a power of 2. 3. Remember what circling means!

8. Application of Karnaugh Maps: The One-bit Adder Adder Cin Cout S B A ABCinSCout 00000 00110 01010 01101 10010 10101 11001 11111 + S = A’B’Cin + A’BCin’ + A’BCin + ABCin Cout = A’BCin + A B’Cin + ABCin’ + ABCin = A’BCin + ABCin + AB’Cin + ABCin + ABCin’ + ABCin = BCin + ACin + AB = (A’ + A)BCin + (B’ + B)ACin + (Cin’ + Cin)AB = 1·BCin + 1· ACin + 1· AB How to use a Karnaugh Map instead of the Algebraic simplification?

9. Application of Karnaugh Maps: The One-bit Adder Adder Cin Cout S B A Karnaugh Map for Cout Now we have to cover all the 1s in the Karnaugh Map using the largest rectangles and as few rectangles as we can. A B Cin 0 0 0 111 0 1

10. A B Application of Karnaugh Maps: The One-bit Adder Adder Cin Cout S B A 0 0 0 0111 1 Karnaugh Map for Cout Now we have to cover all the 1s in the Karnaugh Map using the largest rectangles and as few rectangles as we can. Cout = ACin

11. A B Cin Application of Karnaugh Maps: The One-bit Adder Adder Cin Cout S B A 0 0 0 0111 1 Karnaugh Map for Cout Now we have to cover all the 1s in the Karnaugh Map using the largest rectangles and as few rectangles as we can. Cout = Acin + AB

12. A B Cin Application of Karnaugh Maps: The One-bit Adder Adder Cin Cout S B A 0 0 0 0111 1 Karnaugh Map for Cout Now we have to cover all the 1s in the Karnaugh Map using the largest rectangles and as few rectangles as we can. Cout = ACin + AB + BCin

13. A B Cin Application of Karnaugh Maps: The One-bit Adder Adder Cin Cout S B A 0 1 110 01 0 Karnaugh Map for S S = A’BCin’

14. A B Cin Application of Karnaugh Maps: The One-bit Adder Adder Cin Cout S B A 0 1 110 01 0 Karnaugh Map for S S = A’BCin’ + A’B’Cin

15. A B Cin Application of Karnaugh Maps: The One-bit Adder Adder Cin Cout S B A 0 1 110 01 0 Karnaugh Map for S S = A’BCin’ + A’B’Cin + ABCin

16. A B Cin Application of Karnaugh Maps: The One-bit Adder Adder Cin Cout S B A 0 1 110 01 0 Karnaugh Map for S S = A’BCin’ + A’B’Cin + ABCin + AB’Cin’ No Possible Reduction! Can you draw the circuit diagrams?

17. Karnaugh Maps for Four Input Functions °Represent functions of 4 inputs with 16 minterms °Use same rules developed for 3-input functions °Note bracketed sections shown in example.

18. C+ B’D’ Solution set can be considered as a coordinate System! Karnaugh map: 4-variable example °F(A,B,C,D) =  m(0,2,3,5,6,7,8,10,11,14,15) F = D A B A B C D 0000 1111 1000 0111 10011001 010001000 11 11 C + A’BD

19. A' B' D + A' C + B' C D B C' D' + A C' + A B D' LT= EQ= GT= K-map for LTK-map for GT Design examples 0 00100010 00 D A11 010001000 B C K-map for EQ 10011001 00 D A00 10011001 B C 010001000 11 D A00 0 00100010 B C Can you draw the truth table for these examples? A'B'C'D' + A'BC'D + ABCD + AB'CD’

20. ABCDABCD EQ Physical Implementation °Step 1: Truth table °Step 2: K-map °Step 3: Minimized sum-of- products °Step 4: Physical implementation with gates K-map for EQ 10011001 00 D A00 10011001 B C

21. Karnaugh Maps °Four variable maps. F=BC +CD + AC+ AD 0 AB 11 0 0001 00 01 CD 0 01 1 1110 F=ABC + ACD + ABC + AB CD + ABC + AB C 1 10 1 11 10 1 11 1 °Need to make sure all 1’s are covered °Try to minimize total product terms. °Design could be implemented using NANDs and NORs

22. 5-Variable K-Map 101198 13141512 5674 1230 BC DE 26 27 25 24 30 31 29 28 22 23 21 20 18 19 17 16 BC DE A=0 A=1 A’BCDE’ ABCDE’

23. Karnaugh maps: Don’t cares °In some cases, outputs are undefined °We “don’t care” if the logic produces a 0 or a 1 °This knowledge can be used to simplify functions. 01 X0X1X0X1 D A 1 110X110X 00 B C CD AB 00 01 11 10 00 01 11 10 - Treat X’s like either 1’s or 0’s - Very useful - OK to leave some X’s uncovered

24. + C’D Karnaugh maps: Don’t cares °f(A,B,C,D) =  m(1,3,5,7,9) + d(6,12,13) without don't cares -f = 01 X0X1X0X1 D A 1 110X110X 00 B C A’D CD AB 00 01 11 10 00 01 11 10 Cf 00 01 10 11 00 01 1X 100110011100110011 D 0 1 0 1 0 1 0 101010101101010101 10100XX0010100XX00 A 0 0 0 0 0 0 0 011111111011111111 + B 0 0 0 0 1 1 1 100001111100001111 +

25. Don’t Care Conditions °In some situations, we don’t care about the value of a function for certain combinations of the variables. these combinations may be impossible in certain contexts or the value of the function may not matter in when the combinations occur °In such situations we say the function is incompletely specified and there are multiple (completely specified) logic functions that can be used in the design. so we can select a function that gives the simplest circuit °When constructing the terms in the simplification procedure, we can choose to either cover or not cover the don’t care conditions.

26. Map Simplification with Don’t Cares F=ACD+B+AC 0 AB xx 1 0001 00 01 CD 0 x1 0 1110 1 x0 1 11 10 1 11 x 0 AB xx 1 0001 00 01 CD 0 x1 0 1110 1 x0 1 11 10 1 11 x F=ABCD+ABC+BC+AC °Alternative covering.

27. Karnaugh maps: don’t cares (cont’d) °f(A,B,C,D) =  m(1,3,5,7,9) + d(6,12,13) f = A'D + B'C'Dwithout don't cares f = with don't cares don't cares can be treated as 1s or 0s depending on which is more advantageous 01 X0X1X0X1 D A1 110X110X 00 B C A'D by using don't care as a "1" a 2-cube can be formed rather than a 1-cube to cover this node + C'D

28. Definition of terms for two-level simplification °Implicant Single product term of the ON-set (terms that create a logic 1) °Prime implicant Implicant that can't be combined with another to form an implicant with fewer literals. °Essential prime implicant Prime implicant is essential if it alone covers a minterm in the K-map Remember that all squares marked with 1 must be covered °Objective: Grow implicant into prime implicants (minimize literals per term) Cover the K-map with as few prime implicants as possible (minimize number of product terms)

29. 0X110X111 10101010 D A 100010000 11 B C 5 prime implicants: BD, ABC', ACD, A'BC, A'C'D Examples to illustrate terms 01 10101010 D A 01010101 10 B C 6 prime implicants: A'B'D, BC', AC, A'C'D, AB, B'CD minimum cover: AC + BC' + A'B'D essential minimum cover: 4 essential implicants essential

30. Prime Implicants Any single 1 or group of 1s in the Karnaugh map of a function F is an implicant of F. A product term is called a prime implicant of F if it cannot be combined with another term to eliminate a variable. B C A 1 1 1 11 11 1 D Example: If a function F is represented by this Karnaugh Map. Which of the following terms are implicants of F, and which ones are prime implicants of F? (a) AC’D’ (b) BD (c) A’B’C’D’ (d) AC’ (e) B’C’D’ Implicants: (a),(c),(d),(e) Prime Implicants: (d),(e)

31. Essential Prime Implicants A product term is an essential prime implicant if there is a minterm that is only covered by that prime implicant. - The minimal sum-of-products form of F must include all the essential prime implicants of F.

32. NAND-NAND & NOR-NOR Networks DeMorgan’s Law: (a + b)’ = a’ b’ (a b)’ = a’ + b’ a + b = (a’ b’)’ (a b) = (a’ + b’)’ push bubbles or introduce in pairs or remove pairs.

33. NAND-NAND Networks °Mapping from AND/OR to NAND/NAND

34. Implementations of Two-level Logic °Sum-of-products AND gates to form product terms (minterms) OR gate to form sum °Product-of-sums OR gates to form sum terms (maxterms) AND gates to form product

35. Two-level Logic using NAND Gates °Replace minterm AND gates with NAND gates °Place compensating inversion at inputs of OR gate

36. Two-level Logic using NAND Gates (cont’d) °OR gate with inverted inputs is a NAND gate de Morgan's:A' + B' = (A B)' °Two-level NAND-NAND network Inverted inputs are not counted In a typical circuit, inversion is done once and signal distributed

37. Conversion Between Forms °Convert from networks of ANDs and ORs to networks of NANDs and NORs Introduce appropriate inversions ("bubbles") °Each introduced "bubble" must be matched by a corresponding "bubble" Conservation of inversions Do not alter logic function °Example: AND/OR to NAND/NAND A B C D Z A B C D Z NAND

38. Z = [ (A B)' (C D)' ]' = [ (A' + B') (C' + D') ]' = [ (A' + B')' + (C' + D')' ] = (A B) + (C D) Conversion Between Forms (cont’d) °Example: verify equivalence of two forms A B C D Z A B C D Z NAND

39. Conversion to NAND Gates °Start with SOP (Sum of Products) circle 1s in K-maps °Find network of OR and AND gates

40. ABCDEFGABCDEFG X Multi-level Logic °x = A D F + A E F + B D F + B E F + C D F + C E F + G Reduced sum-of-products form – already simplified 6 x 3-input AND gates + 1 x 7-input OR gate (may not exist!) 25 wires (19 literals plus 6 internal wires) °x = (A + B + C) (D + E) F + G Factored form – not written as two-level S-o-P 1 x 3-input OR gate, 2 x 2-input OR gates, 1 x 3-input AND gate 10 wires (7 literals plus 3 internal wires)

41. Level 1Level 2Level 3Level 4 original AND-OR network A C D B B C’ F introduction and conservation of bubbles A C D B B C’ F redrawn in terms of conventional NAND gates A C D B’ B C’ F Conversion of Multi-level Logic to NAND Gates °F = A (B + C D) + B C'

42. A X B C D F (a) Original circuit A X B C D F (b) Add double bubbles at inputs D’ A X’ B C F (c) Distribute bubbles some mismatches D’ A X B C F X’ (d) Insert inverters to fix mismatches Conversion Between Forms °Example

43. Exclusive-OR and Exclusive-NOR Circuits Exclusive-OR (XOR) produces a HIGH output whenever the two inputs are at opposite levels.

44. Exclusive-NOR (XNOR) : Exclusive-NOR (XNOR) produces a HIGH output whenever the two inputs are at the same level. Exclusive-NOR Circuits

45. XNOR gate may be used to simplify circuit implementation. Exclusive-NOR Circuits

46. XOR Function °XOR function can also be implemented with AND/OR gates (also NANDs).

47. XOR Function °Even function – even number of inputs are 1. °Odd function – odd number of inputs are 1.

48. FIGURE 4-25 XOR gates used to implement the parity generator and the parity checker for an even-parity system. Parity Generation and Checking

49. °Important concept – analyze digital circuits Given a circuit -Create a truth table -Create a minimized circuit °Approaches Boolean expression approach Truth table approach °Leads to minimized hardware °Provides insights on how to design hardware Tie in with K-maps (next time) Digital Circuit Analysis

50. The Problem °How can we convert from a circuit drawing to an equation or truth table? °Two approaches °Create intermediate equations °Create intermediate truth tables A B C A B C’ Out

51. Label Gate Outputs 1.Label all gate outputs that are a function of input variables. 2.Label gates that are a function of input variables and previously labeled gates. 3.Repeat process until all outputs are labelled. A B C A B C’ Out R S T

52. Approach 1: Create Intermediate Equations  Step 1: Create an equation for each gate output based on its input. R = ABC S = A + B T = C’S Out = R + T A B C A B C’ Out R S T

53. Approach 1: Substitute in subexpressions  Step 2: Form a relationship based on input variables (A, B, C) R = ABC S = A + B T = C’S = C’(A + B) Out = R+T = ABC + C’(A+B) A B C A B C’ Out R S T

54. Approach 1: Substitute in subexpressions  Step 3: Expand equation to SOP final result Out = ABC + C’(A+B) = ABC + AC’ + BC’ A C’ Out B C’ A B C

55. Approach 2: Truth Table  Step 1: Determine outputs for functions of input variables. A00001111A00001111 B00110011B00110011 C01010101C01010101 R00000001R00000001 S00111111S00111111 A B C A B C’ Out R S T

56. Approach 2: Truth Table  Step 2: Determine outputs for functions of intermediate variables. A00001111A00001111 B00110011B00110011 C01010101C01010101 T = S * C’ R00000001R00000001 S00111111S00111111 T00101010T00101010 C’ 1 0 1 0 1 0 1 0 A B C A B C’ Out R S T

57. Approach 2: Truth Table  Step 3: Determine outputs for function. A00001111A00001111 B00110011B00110011 C01010101C01010101 R00000001R00000001 S00111111S00111111 T00101010T00101010 Out 0 1 0 1 0 1 R + T = Out A B C A B C’ Out R S T

58. More Difficult Example  Step 3: Note labels on interior nodes

59. More Difficult Example: Truth Table  Remember to determine intermediate variables starting from the inputs.  When all inputs determined for a gate, determine output.  The truth table can be reduced using K-maps. A00001111A00001111 B00110011B00110011 C01010101C01010101 F200010111F200010111 F’ 2 1 0 1 0 T101111111T101111111 T200000001T200000001 T301101000T301101000 F101101001F101101001

60. Summary °Important to be able to convert circuits into truth table and equation form WHY? ---- leads to minimized sum of product representation °Two approaches illustrated Approach 1: Create an equation with circuit output dependent on circuit inputs Approach 2: Create a truth table which shows relationship between circuit inputs and circuit outputs °Both results can then be minimized using K-maps. °Next time: develop a minimized SOP representation from a high level description