ARTIST2 Network of Excellence on Embedded Systems Design cluster meeting –Bologna, May 22 nd, 2006 System Modelling Infrastructure Activity leader : Jan Madsen (DTU) ARTIST2 – Cluster Meeting Bologna, May 22 nd, 2006 Activity Execution Platforms

ARTIST2 Network of Excellence on Embedded Systems Design cluster meeting –Bologna, May 22 nd, 2006 Year 1 activities Achievements: Our integration work UNIBO Braunschweig ETH Zürich DTU ESI Univ. Notre Dame First steps: PISA PISA Hierarchical + dynamic priority scheduling Power model + optimization High-level models for shared communication Hybrid functional and formal models Traffic generator model + mixed level simulation SymTA/S Linköping Hierarchical scheduling + simulation

ARTIST2 Network of Excellence on Embedded Systems Design cluster meeting –Bologna, May 22 nd, 2006 Year 2 activities Research related to DTU UNIBO Braunschweig ETH Zürich DTU ESI Univ. Notre Dame First steps: PISA PISA Hierarchical + dynamic priority scheduling Power model + optimization High-level models for shared communication Hybrid functional and formal models Traffic generator model + mixed level simulation SymTA/S Linköping Hierarchical scheduling + simulation AAU UPPAAL

ARTIST2 Network of Excellence on Embedded Systems Design cluster meeting –Bologna, May 22 nd, 2006 ARTS Framework  ARTS Simulation framework based on SystemC  ARTS PE module:  Application  OS  IO ports (OCP 2.0 interface)  IO device drivers  ARTS Communication module:  Network topology and protocol  Network adapters  IO ports (OCP 2.0 interface)  Applications of ARTS :  MPSoC (NoC exploration)  Wireless sensor networks  Automotive systems (TT vs. ET)  Dynamic reconfiguration  IO Master OCP IO device Slave HW model Synchronnizer Resource Allocator Scheduler  1  n... A p p l i c a t i o n R T O S SoC communication interface(OCP)

ARTIST2 Network of Excellence on Embedded Systems Design cluster meeting –Bologna, May 22 nd, 2006 Outline of presentation  ARTS / MPARM  ARTS for automotive  ARTS exploration using PISA/ETHZ  ARTS UPPAAL

ARTIST2 Network of Excellence on Embedded Systems Design cluster meeting –Bologna, May 22 nd, 2006 ARTS / MPARM  Interactions between Univ. of Bologna and DTU  Traffic generators  ARTS – MPARM interaction for mixed level simulation

ARTIST2 Network of Excellence on Embedded Systems Design cluster meeting –Bologna, May 22 nd, 2006 RIPE ni IP core ni IP core ARTS NoC (from ARTS, TLM, CC, RTL) CC ni OCP Interface IP EmulatorIP ISS System Integration Overview

ARTIST2 Network of Excellence on Embedded Systems Design cluster meeting –Bologna, May 22 nd, 2006 ni IP core ni IP core ARTS AMBA-AHB ni OCP Interface Exploration with AMBA-AHB AMBA Interface TL1 TL0 Need two types of adapter (i) abstraction and (ii) protocol

ARTIST2 Network of Excellence on Embedded Systems Design cluster meeting –Bologna, May 22 nd, 2006 master IP core ARTS AMBA-AHB master OCP Interface Exploration with AMBA-AHB AMBA Interface TL1 TL0 Adapter slave Adapter

ARTIST2 Network of Excellence on Embedded Systems Design cluster meeting –Bologna, May 22 nd, 2006 ARTS Master OCP Interface ARTS Module MPARM to MPARM Interconnect OCP-IP Channel Package

ARTIST2 Network of Excellence on Embedded Systems Design cluster meeting –Bologna, May 22 nd, 2006 ARTS Slave OCP Interface ARTS Module MPARM to MPARM Interconnect OCP-IP Channel Package

ARTIST2 Network of Excellence on Embedded Systems Design cluster meeting –Bologna, May 22 nd, 2006 ARTS for automotive  TU Linkoping has extended ARTS  No global clock for time reference  Possible to execute real code  Implemented a number of automotive network protocols

ARTIST2 Network of Excellence on Embedded Systems Design cluster meeting –Bologna, May 22 nd, 2006 ARTS exploration using PISA/ETHZ  Multiobjective optimization problem  Using the PISA framework from ETHZ (SPEA2) ApplicationArchitecture Mapping Performance analysis Performance numbers Re-mapping Architecture improvements Rewrite Application

ARTIST2 Network of Excellence on Embedded Systems Design cluster meeting –Bologna, May 22 nd, 2006 Design space exploration ASIC0FPGAASIC0 BB GPP0 mapping  Meet deadlines  Min. power  Min. buffer sizes  Component cost  Hyper period  Total number of tasks 530 Static scheduling

ARTIST2 Network of Excellence on Embedded Systems Design cluster meeting –Bologna, May 22 nd, 2006 Scenarios  Explore task mappings  No change in architecture  Explore task mappings and architecture improvements  Number and types of cores buses and bus bridges ASIC0 FPGAASIC0 BB GPP0 PEGPP0GPP1GPP2FPGAASIC0ASIC1BUS Frequency (MHz) Cost ($)

ARTIST2 Network of Excellence on Embedded Systems Design cluster meeting –Bologna, May 22 nd, 2006 Exploring task mappings ASIC0 FPGAASIC0 BB GPP0 A0A1 Cores88 Cost ($)2045 Energy (mJ) Total buffer Max buffer

ARTIST2 Network of Excellence on Embedded Systems Design cluster meeting –Bologna, May 22 nd, Architecture improvements GPP2 BB ASIC1 GPP1 ASIC1 ASIC0 GPP1 B B ASIC1 GPP2 ASIC1ASIC0 A1A2A3 Cores856 Cost ($) Energy (mJ) Total buffer Max buffer

ARTIST2 Network of Excellence on Embedded Systems Design cluster meeting –Bologna, May 22 nd, 2006 ARTS UPPAAL Application layer Middelware layer Processing element layer Network layer A layered collection of event-triggered timed automatons

ARTIST2 Network of Excellence on Embedded Systems Design cluster meeting –Bologna, May 22 nd, 2006 ARTS UPPAAL model UPPAAL task model UPPAAL scheduling model

ARTIST2 Network of Excellence on Embedded Systems Design cluster meeting –Bologna, May 22 nd, 2006 Preliminary results  Task model  Schedulers  RM  EDF  Experiments  2-8 tasks on 1-2 processor verified in 1-30 sec.

ARTIST2 Network of Excellence on Embedded Systems Design cluster meeting –Bologna, May 22 nd, 2006 System Modelling Infrastructure  Focus of year 2:  Integration of models  Results:  MPARM and RT-Calculus using Trafficgenerators (DATE’06)  ARTS and UPPAAL  More ?