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1 Oct 2, 2003 Design Optimization of Mixed Time/Event-Triggered Distributed Embedded Systems Traian Pop, Petru Eles, Zebo Peng Embedded Systems Laboratory.

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Presentation on theme: "1 Oct 2, 2003 Design Optimization of Mixed Time/Event-Triggered Distributed Embedded Systems Traian Pop, Petru Eles, Zebo Peng Embedded Systems Laboratory."— Presentation transcript:

1 1 Oct 2, 2003 Design Optimization of Mixed Time/Event-Triggered Distributed Embedded Systems Traian Pop, Petru Eles, Zebo Peng Embedded Systems Laboratory Computer and Information Science Dept. Linköpings universitet, Sweden

2 Design Optimization of Mixed Time/Event-Triggered Distributed Embedded Systems Traian Pop, Petru Eles, Zebo Peng 2 Oct 2, 2003 Introduction Node 1 Node 2 Node 3 Hard real-time constraints (e.g. X-by-wire)... Factory Systems NoCs Automotive Electronics

3 Design Optimization of Mixed Time/Event-Triggered Distributed Embedded Systems Traian Pop, Petru Eles, Zebo Peng 3 Oct 2, 2003 Introduction (cont’d) Node 1 Node 2 Node 3 CAN TTP Time-Triggered (TT) Scheduling Event-Triggered (ET) Scheduling

4 Design Optimization of Mixed Time/Event-Triggered Distributed Embedded Systems Traian Pop, Petru Eles, Zebo Peng 4 Oct 2, 2003 Introduction (cont’d) Node 1 Node 2 Node 3 Time-Triggered Functionality Event-Triggered Functionality Static (ST) communication ST/DYN Bus access cycle Dynamic (DYN) communication

5 Design Optimization of Mixed Time/Event-Triggered Distributed Embedded Systems Traian Pop, Petru Eles, Zebo Peng 5 Oct 2, 2003 Our Contribution Design of distributed hard real-time embedded systems Mixed ET and TT task sets Universal Communication Model: representation of mixed ST/DYN communication protocol over the bus Our focus: Scheduling and timing analysis for such systems [ CODES’02 ] Specific design problems Design optimization heuristic

6 Design Optimization of Mixed Time/Event-Triggered Distributed Embedded Systems Traian Pop, Petru Eles, Zebo Peng 6 Oct 2, 2003 Outline Introduction System Model Scheduling and Schedulability Analysis Specific Design Problems and Design Optimization Heuristic Conclusions

7 Design Optimization of Mixed Time/Event-Triggered Distributed Embedded Systems Traian Pop, Petru Eles, Zebo Peng 7 Oct 2, 2003 static phase dynamic phase dynamic phase Hardware Architecture ST/DYN bus Node 1 Node 2 Node 3 CPU I/O ROM communication controller RAM slot 1 slot 2 slot 3 slot 1slot 2 slot 3 T bus

8 Design Optimization of Mixed Time/Event-Triggered Distributed Embedded Systems Traian Pop, Petru Eles, Zebo Peng 8 Oct 2, 2003 Application Model Task graphs Domains for tasks: either TT or ET Domains for messages: either ST or DYN Task attributes: Processor, Worst-Case Execution Time(C i ), Period, Deadline, Priority Message attributes: Sender, Worst-Case Transmission Time, Period, Deadline, Priority

9 Design Optimization of Mixed Time/Event-Triggered Distributed Embedded Systems Traian Pop, Petru Eles, Zebo Peng 9 Oct 2, 2003 Software Architecture Real-time kernel which supports both ET and TT activities Static cyclic scheduling for TT activities Fixed-priority scheduling for ET activities Schedule Table Prioritized Ready List

10 Design Optimization of Mixed Time/Event-Triggered Distributed Embedded Systems Traian Pop, Petru Eles, Zebo Peng 10 Oct 2, 2003 Introduction System Model Scheduling and Schedulability Analysis Specific Design Problems and Design Optimization Heuristic Conclusions Outline

11 Design Optimization of Mixed Time/Event-Triggered Distributed Embedded Systems Traian Pop, Petru Eles, Zebo Peng 11 Oct 2, 2003 Holistic Scheduling Schedulability analysis Static scheduling Ri Di ?Ri Di ? Valid static schedule OUTPUTS TT tasks ST messages ET tasks DYN messages INPUTS [CODES’2002]

12 Design Optimization of Mixed Time/Event-Triggered Distributed Embedded Systems Traian Pop, Petru Eles, Zebo Peng 12 Oct 2, 2003 Outline Introduction System Model Scheduling and Schedulability Analysis Specific Design Problems and Design Optimization Heuristic Conclusions

13 Design Optimization of Mixed Time/Event-Triggered Distributed Embedded Systems Traian Pop, Petru Eles, Zebo Peng 13 Oct 2, 2003 Specific Design Problems Partitioning of functionality into TT/ET domains Optimization of the ST/DYN bus access cycle ST/DYN Bus access cycle

14 Design Optimization of Mixed Time/Event-Triggered Distributed Embedded Systems Traian Pop, Petru Eles, Zebo Peng 14 Oct 2, 2003 Mapping Partitioning of the system functionality: Tasks: TT or ET ? Messages: ST or DYN ? Partitioning and Mapping

15 Design Optimization of Mixed Time/Event-Triggered Distributed Embedded Systems Traian Pop, Petru Eles, Zebo Peng 15 Oct 2, 2003 Partitioning of Functionality Node 1 Node 2       Node 1 Node 2 Node 1 Node 2    D2D2 D3D3 Node 1 Node 2    

16 Design Optimization of Mixed Time/Event-Triggered Distributed Embedded Systems Traian Pop, Petru Eles, Zebo Peng 16 Oct 2, 2003 Optimization of Bus Access Cycle Determining the optimal structure of the bus access cycle Number, length and order of the ST/DYN phases Static phase 1 Static phase 2 Static phase 3 Dynamic phase 2 Dynamic phase 1 Bus access cycle

17 Design Optimization of Mixed Time/Event-Triggered Distributed Embedded Systems Traian Pop, Petru Eles, Zebo Peng 17 Oct 2, 2003 Slot 1 Slot 2 DYN Node 1 Node 2 Bus   m Bus cycle Optimization of Bus Access Cycle Slot 1 Slot 2 DYN Node 1 Node 2 Bus  m Bus cycle  Slot 1 Slot 2 DYN Node 1 Node 2 Bus   m Bus cycle Slot 1 Slot 2 DYN Node 1 Node 2 Bus   m Bus cycle Slot 1 Slot 2 DYN Node 1 Node 2 Bus  m Bus cycle  D2D2

18 Design Optimization of Mixed Time/Event-Triggered Distributed Embedded Systems Traian Pop, Petru Eles, Zebo Peng 18 Oct 2, 2003 Problem Definition Input: Specification of a TT/ET Distributed Embedded System Some tasks are not mapped Some task graphs are not assigned to any of TT/ET domains Output: System configuration TT/ET partitioning Structure of the ST/DYN Bus Cycle Mapping of functionality on the nodes Timing constraints of the application are satisfied

19 Design Optimization of Mixed Time/Event-Triggered Distributed Embedded Systems Traian Pop, Petru Eles, Zebo Peng 19 Oct 2, 2003 Optimization Heuristic Step 0: Straightforward configuration Step 1: Modify Initial Configuration unschedulable TT partition Step 3: Bus Access Optimization unschedulable ET partition Step 2: Mapping and Partitioning unschedulable ET partition Greedy assignment of tasks and messages to nodes and TT/ET domains Exploration of various structures of the bus access cycle Schedulable system

20 Design Optimization of Mixed Time/Event-Triggered Distributed Embedded Systems Traian Pop, Petru Eles, Zebo Peng 20 Oct 2, 2003 Schedulable Applications 6 nodes 40 applications / set 60% processor utilisation

21 Design Optimization of Mixed Time/Event-Triggered Distributed Embedded Systems Traian Pop, Petru Eles, Zebo Peng 21 Oct 2, 2003 Schedulable Applications 60-100 tasks mapped on 4-6 nodes 12-20 task graphs

22 Design Optimization of Mixed Time/Event-Triggered Distributed Embedded Systems Traian Pop, Petru Eles, Zebo Peng 22 Oct 2, 2003 Real-Life Example Node 1 Node 2 Node 3 Node 4 Node 5 CC: 42 tasks, 11 task-graphs - 1 TT task-graph - 10 unpartitioned task-graphs - 10 unmapped tasks ABS: 35 ET tasks, already mapped Schedulable solution: 2 ET and 8 TT task-graphs

23 Design Optimization of Mixed Time/Event-Triggered Distributed Embedded Systems Traian Pop, Petru Eles, Zebo Peng 23 Oct 2, 2003 Conclusions Distributed embedded systems with mixed TT/ET tasks sets ST/DYN communication protocols Specific design issues TT/ET partitioning Optimization of the ST/DYN Bus Cycle Optimization Heuristic + mapping of functionality on the nodes + timing constraints are satisfied

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