1 of 14 1 Analysis and Synthesis of Communication-Intensive Heterogeneous Real-Time Systems Paul Pop Computer and Information Science Dept. Linköpings universitet

2 of 14 2  Introduction  System-level design and modeling  Conditional process graph  The system platform  Time-driven vs. event-driven systems  Communication-intensive heterogeneous real-time systems  Time-driven systems  Scheduling and bus access optimization  Incremental mapping  Event-driven systems  Schedulability analysis and bus access optimization  Incremental mapping  Multi-Cluster Systems  Schedulability analysis and bus access optimization  Frame packing  Summary of contributions Outline

3 of 14 3 General purpose systemsEmbedded systems Microprocessor market shares Embedded Systems Communication-intensive heterogeneous real-time systems

4 of 14 4 Embedded Systems Characteristics  Dedicated functionality (not general purpose computers)  Embedded into a host system  Complex architectures  Embedded systems design constraints  Correct functionality  Performance, timing constraints: real-time systems  Development cost, unit cost, size, power, flexibility, time-to- prototype, time-to-market, maintainability, correctness, safety, etc.  Difficult to design, analyze and implement  System-level design  Reuse and flexibility

5 of 14 5 System-Level Design System specification Software model Hardware model Software generation Hardware synthesis Software blocks Hardware blocks Prototype Fabrication System-level design tasks In this thesis  Scheduling  Bus access optimization  Mapping

6 of 14 6 P4P4 P4P4 P5P5 P5P5 P7P7 P7P7 P 13 P 15 First processor Second processor ASIC C C DD P0P0 P 18 P1P1 P1P1 P2P2 P2P2 P3P3 P3P3 P6P6 P6P6 P8P8 P8P8 P9P9 P9P9 P 10 P 11 P 12 P 14 P 16 P 17 C K K Application Modeling P0P0 P 18 P1P1 P2P2 P3P3 P6P6 P8P8 P9P9 P 10 P 11 P 12 P 14 P 16 P 17 Subgraph corresponding to D  C  K

7 of I/O Interface Comm. controller CPU RAM ROM ASIC Hardware Platform S0S0 S1S1 S2S2 SGSG S0S0 S1S1 S2S2 SGSG TDMA Round Cycle of two rounds Slot Time Triggered Protocol (TTP)  Bus access scheme: time-division multiple-access (TDMA)  Schedule table located in each TTP controller: message descriptor list (MEDL) Controller Area Network (CAN)  Priority bus, collision avoidance  Highest priority message wins the contention  Priorities encoded in the frame identifier Cluster: one network Gateway

8 of 14 8 Distributed Safety-Critical Applications...  Distributed applications are difficult to...  Analyze (e.g., guaranteeing timing constraints)  Design (e.g., efficient implementation)  Distributed applications  On a single cluster  On several clusters  Motivation  Reduce costs: use resources efficiently  Requirements: close to sensors/ actuators

9 of 14 9 Event-Driven vs. Time-Driven Systems  Event-driven systems  Activation of processes is done at the occurrence of significant events  Scheduling event-triggered activities  Fixed-priority preemptive scheduling  Response time analysis: calculate worst-case response times for each process  Schedulability test: response times smaller than the deadlines  Time-driven systems  Activation of processes is done at predefined points in time  Scheduling time-triggered activities  Static cyclic non-preemptive scheduling  Building a schedule table: static cyclic scheduling (e.g., list scheduling)

10 of  Introduction  System-level design and modeling  Conditional process graph  The system platform  Time-triggered vs. event-triggered  Communication-intensive heterogeneous real-time systems  Time-driven systems  Scheduling and bus access optimization  Incremental mapping  Event-driven systems  Schedulability analysis and bus access optimization  Incremental mapping  Multi-Cluster Systems  Schedulability analysis and bus access optimization  Frame packing  Summary of contributions Outline

11 of Scheduling and Bus Access Optimization  Input  Safety-critical application: set of conditional process graphs  The worst-case execution time of each process  The size of each messages  The system architecture and mapping are given  Time-driven systems  Single-cluster architecture  Time-triggered protocol  Non-preemptive static cyclic scheduling  Output  Design implementation such that the application is schedulable and execution delay is minimized  Local schedule tables for each node  The sequence and size of the slots in a TDMA round  The MEDL (schedule table for messages) for each TTP controller Communication infrastructure parameters Time-driven systems

12 of P1P1 P1P1 P4P4 P4P4 P2P2 P2P2 P3P3 P3P3 m1m1 m2m2 m3m3 m4m4 S1S1 S0S0 Round 1Round 2Round 3Round 4Round 5 P1P1 P4P4 P2P2 m1m1 m2m2 m3m3 m4m4 P3P3 24 ms Round 1 P1P1 Round 2Round 3Round 4 S1S1 S0S0 m1m1 m2m2 m3m3 m4m4 P2P2 P3P3 P4P4 22 ms Round 1Round 2Round 3 S1S1 S0S0 P2P2 P3P3 P4P4 P1P1 m1m1 m2m2 m3m3 m4m4 20 ms Scheduling and Optimization Example Time-driven systems

13 of Scheduling and Optimization Strategy  List scheduling based algorithm  The scheduling algorithm has to take into consideration the TTP  Priority function for the list scheduling  Bus access optimization heuristics  Greedy heuristic, two variants  Greedy 1 tries all possible slot lengths  Greedy 2 uses feedback from the scheduling algorithm  Simulated Annealing  Produces near-optimal solutions in a very large time  Cannot be used inside a design space exploration loop  Used as the baseline for comparisons  Straightforward solution  Finds a schedulable application  Does not consider the optimization of the design Time-driven systems

14 of Number of processes Average Percentage Deviation [%] Can We Improve the Schedules? Baseline: Simulated Annealing Cost function: schedule length  Case study  Vehicle cruise controller  Used throughout the thesis Time-driven systems

15 of S1S1 S0S0 Round 1Round 2Round 3Round 4Round 5 P1P1 P4P4 P2P2 m1m1 m2m2 m3m3 m4m4 P3P3 P1P1 P4P4 P2P2 P3P3 N1N1 N2N2 N1N1 N2N2 Bus “Classic” Mapping and Scheduling Example Time-driven systems

16 of  Start from an already existing system with applications  In practice, very uncommon to start from scratch  Implement new functionality on this system (increment)  As few as possible modifications of the existing applications, to reduce design and testing time  Plan for the next increment: It should be easy to add functionality in the future Incremental Design Process Time-driven systems

17 of Minimal modifications are performed to the existing applications Existing applications N-1 Map and schedule so that the future applications will have a chance to fit Current applications N Do not exist yet at Version N! Future applications Version N+1 Incremental Mapping and Scheduling Time-driven systems

18 of Incremental Mapping and Scheduling  Input  A set of existing applications modeled using process graphs  A current application to be mapped modeled using process graphs  Each process graph in an application has its own period and deadline  Each process has a potential set of nodes to be mapped on and a WCET  Characteristics of the future applications  The system architecture is given  Output  A mapping and scheduling of the current application, such that:  Requirement (a) constraints of the current application are satisfied and minimal modifications are performed to the existing applications  Requirement (b) new future applications can be mapped on the resulted system Time-driven systems

19 of Existing application Current application Future application The future application does not fit! (a)(b) Mapping and Scheduling Example Time-driven systems

20 of Mapping and Scheduling Strategies Time-driven systems  Design optimization problem  Design criteria reflect the degree to which a design supports an incremental design process  Design metrics quantify the degree to which the criteria are met  Heuristics to improve the design metrics  Ad-hoc approach  Little support for incremental design  Mapping Heuristic  Iteratively performs design transformations that improve the design

21 of % of future applications mapped existing applications: 400, future application: 80 Number of processes in the current application Are the mapping strategies proposed facilitating the implementation of future applications? Existing application Current application Future application Can We Support Incremental Design? Time-driven systems

22 of  Introduction  System-level design and modeling  Conditional process graph  The system platform  Time-triggered vs. event-triggered  Communication-intensive heterogeneous real-time systems  Time-driven systems  Scheduling and bus access optimization  Incremental mapping  Event-driven systems  Schedulability analysis and bus access optimization  Incremental mapping  Multi-Cluster Systems  Schedulability analysis and bus access optimization  Frame packing  Summary of contributions Outline

23 of Scheduling and Bus Access Optimization  Input  Safety-critical application: set of conditional process graphs  The worst-case execution time of each process  The size of each messages  The system architecture and mapping are given  Event-driven systems  Single cluster architecture  Time-triggered protocol  Fixed-priority preemptive scheduling  Output  Worst-case response times (schedulability analysis)  Design implementation such that the application is schedulable and execution delay is minimized  The sequence and size of the slots in a TDMA round  The MEDL (schedule table for messages) for each TTP controller Communication infrastructure parameters Event-driven systems

24 of Conditional Process Graph Scheduling P3P3 P3P3 P5P5 P5P5 C P0P0 P0P0 P1P1 P1P1 P6P6 P6P6 P2P2 P2P2 P7P7 P7P7 P4P4 P4P4 P8P8 P8P8 C G1G1 P 11 P 12 P9P9 P9P9 P G2G2 Deadline: 110 Event-driven systems

25 of Single message per frame, allocated statically: Static Single Message Allocation 2. Several messages per frame, allocated statically: Static Multiple Message Allocation m1m1 m2m2 m5m5 m3m3 m4m4 Round 1Round 2Round 3 S0S0 S1S1 messages are dynamically produced by the processes frames are statically determined by the MEDL 3. Several messages per frame, allocated dynamically: Dynamic Message Allocation 4. Several messages per frame, split into packets, allocated dynamically Dynamic Packets Allocation Scheduling of Messages using the TTP Event-driven systems

26 of Compartison… Dynamic Messages Single Message Dynamic Packets Multiple Messages Average Percentage Deviation [%] Number of processes Cost function: degree of schedulability Event-driven systems

27 of m1m1 m2m2 P1P1 P2P2 P3P3 m2m2 m1m1 P1P1 P2P2 P3P3 Swapping m 1 with m 2 : all processes meet their deadlines. m1m1 m2m2 P1P1 P2P2 P3P3 Putting m 1 and m 2 in the same slot: all processes meet their deadline, the communication delays are reduced. Process P 2 misses its deadline! Optimizing Bus Access (Static Allocation) Event-driven systems

28 of  Introduction  System-level design and modeling  Conditional process graph  The system platform  Time-triggered vs. event-triggered  Communication-intensive heterogeneous real-time systems  Time-driven systems  Scheduling and bus access optimization  Incremental mapping  Event-driven systems  Schedulability analysis and bus access optimization  Incremental mapping  Multi-Cluster Systems  Schedulability analysis and bus access optimization  Frame packing  Summary of contributions Outline

29 of Schedulability Analysis and Optimization  Input  An application modeled as a set of process graphs  Each process has an worst case execution time, a period, and a deadline  Each message has a known size  The system architecture and the mapping of the application are given  Multi-cluster systems  Two-cluster architecture  Time-triggered cluster  Time-triggered protocol  Non-preemptive static cyclic scheduling  Event-triggered cluster  Controller area network protocol  Fixed-priority preemptive scheduling Multi-cluster systems...  Output  Worst case response times and bounds on the buffer sizes  Design implementation such that the application is schedulable and buffer sizes are minimized  Schedule table for TT processes  Priorities for ET processes  Schedule table for TT messages  Priorities for ET messages  TT bus configuration (TDMA slot sequence and sizes) Communication infrastructure parameters System configuration parameters

30 of Multi-Cluster Scheduling  Scheduling cannot be addressed separately for each type of cluster  The inter-cluster communication creates a circular dependency:  TTC static schedules (offsets)  ETC response times  ETC response times  TTC schedule table construction Application, Mapping, Architecture TT Bus Configuration Priorities Schedule Tables Response times Static Scheduling Multi-Cluster Scheduling Offsets Response Times Offset earliest possible start time for an event-triggered activity Bounds on the buffer sizes Response Time Analysis Multi-cluster systems

31 of Optimization Example TTP CAN N1N1 NGNG N2N2 P2P2 P3P3 O3O3 O2O2 m1m1 m3m3 m2m2 SGSG S1S1 SGSG P1P1 S1S1 SGSG P4P4 Deadline missed! TTP CAN N1N1 NGNG N2N2 O3O3 O2O2 m1m1 m3m3 m2m2 S1S1 SGSG SGSG S1S1 SGSG P1P1 P4P4 P2P2 P3P3 Deadline met Transformation: S 1 is the first slot, m 1 and m 2 are sent sooner N1N1 NGNG N2N2 O3O3 O2O2 m1m1 m3m3 m2m2 SGSG S1S1 SGSG S1S1 P1P1 P2P2 P3P3 P4P4 TTP CAN Deadline met Transformation: P 2 is the high priority process on N 2... Multi-cluster systems

32 of Optimization Strategies  OptimizeSchedule  Synthesizes the communication and assigns priorities to obtain a schedulable application  Based on a greedy approach  Cost function: degree of schedulability  OptimizeBuffers  Synthesizes the communication and assigns priorities to reduce the total buffer size  Based on a hill-climbing heuristic  Cost function: total buffer size  Straightforward solution  Finds a schedulable application  Does not consider the optimization of the design Multi-cluster systems

33 of Can We Improve Schedulability? Average Percentage Deviation [%] Number of processes 120 Simulated Annealing Near-optimal values for the degree of schedulability Straightforward solution Does not perform optimizations Cost function: degree of schedulability OptimizeSchedule? OptimizeSchedule

34 of Can We Reduce Buffer Sizes? 0 2k 4k 6k 8k 10k Average total buffer size [k] Number of processes Simulated Annealing Near-optimal values for the total buffer size OptimizeSchedule Does not optimize the total buffer size Cost function: total buffer size OptimizeBuffers? OptimizeBuffers Multi-cluster systems

35 of  Introduction  System-level design and modeling  Conditional process graph  The system platform  Time-triggered vs. event-triggered  Communication-intensive heterogeneous real-time systems  Time-driven systems  Scheduling and bus access optimization  Incremental mapping  Event-driven systems  Schedulability analysis and bus access optimization  Incremental mapping  Multi-Cluster Systems  Schedulability analysis and bus access optimization  Frame packing  Summary of contributions Outline

36 of  Time-driven systems  Static scheduling strategy  Optimization strategies for the synthesis of the bus access scheme  Mapping and scheduling within an incremental design process  Event-driven systems  Schedulability analysis  Optimization strategies for the synthesis of the bus access scheme  Mapping and scheduling within an incremental design process  Multi-cluster systems  Schedulability analysis for multi-cluster systems  Optimization heuristics for system synthesis: minimal buffer sizes needed to run a schedulable application  Frame-packing optimization heuristics Thesis Contributions