S-UTS Toshiyuki Nakano

Non-stop tomographic image taking Use Ultra High Speed Camera Max 100views/sec –Up to 3k frames per second.  Max 100views/sec Image taking by follow shot –No go-stop operation –No go-stop operation to avoid a mechanical bottleneck. –FOV Motion and Blur are canceled by moving lens

Objective lens actuators for S-UTS Made by S.ISHIKAWA Horizontal axis Horizontal + Vertical

S-UTS Camera Image Consist of 32 readout channel Readout SEGMENT 40Mpix/s/ch 504 pixels 512 pixels

Image Filtering and Packing (compression) SUTS Image Pre-processor can accept > 3kfps –Peak data rate ~1.3Gbyte/sec  PCI is 133Mbyte/sec Improved Real Time Filter to reduce uneven light and defocus grains. –16 pipe lines of 32 taps FIR filter using 8 ASIC Filters. –Total 25.6G MAC a second Ring Image Buffer enables to acquire past images. –Possible to acquire after checking grain number. –Relaxing timing constraint. Buffer (packed data storage) capacity is twice as UTS. –Increase capability to enlarge FOV. ASIC FILTER×8+FPGA×16+DSSRAM×8

Arrange readout segments to lines FIR filters Ring frame buffers Spatial filter and Pixel Packing LVDS Camera Interface LVDS Output Interface

Testing Image pre-processor board Image output from this processor

Under Developing Track recognition by TS algorithm Same strategy established in UTS will be applied. To achieve  30 recognition speed, Very Wide Bus by using On-die Memory (build in FPGA) will be used. –8 way interleave  8.0 –Dual port SRAM  2.0 –Main clock 120MHz  200MHz.  1.6  Memory Band Width = 12GByte/sec/chip One CHIP (FPGA) can process 2-3cm 2 /hrs(OPERA) or 0.5-1cm 2 /hrs(DONUT) On-die CPU core can reduce board size and Simplify the design.

LVDS （ 3+1 ）  2 240Mbyte/sec (2.5 msec/view) 32bit Bi-directional FIFO Host interface SLAVE FPGAs Calculating Overlayed Image 0.2msec/view/angle/FPGA Power PC 405  2 Control and Clustering S-UTS Track Recognition Block diagram Block SRAM High band width and Fine Granularity 12.8GByte/sec ＰＰ Ｃ ＳＲＡ Ｍ ＰＰ Ｃ ＳＲＡ Ｍ ＰＰ Ｃ ＳＲＡ Ｍ ＰＰ Ｃ ＳＲＡ Ｍ ＰＰ Ｃ ＳＲＡ Ｍ Rocket IO  10 3Gbyte/sec From Camera Front-end-Processor Local Control BUS MASTER FPGA Reordering Packed Image Controlling Slaves ＰＰ Ｃ ＳＲＡ Ｍ ＰＰ Ｃ ＳＲＡ Ｍ

S-UTS components summary Non stop image taking  ready –objective lens actuator Lens actuator has run for 2month at 60Hz. Minimum life time was cleared. –special stage with good velocity uniformity Deviation from ideal trace < 0.3  m at 60Hz Ultra high speed CCD camera  ready –512  504pixels, 3kframes/sec  1.3Gbytes/sec Light source  ready –New illumination using fiber optics was tested. –It has enough light power of 25mW/φ500  m and enough NA~0.85. Image pre-processor  almost ready –Filtering and packing to supress data rate from 1.3Gbytes/sec ( camera output ) to MBytes/sec ( which can be accepted by track recognition blocks ) –FOV >160×160  m 2 with TIYODA×50, can be enlarged. –Test Scanning with PIEZO system and UTS is possible, to study many parameters. Track recognition Blocks  under developing –Total Memory Band Width will be ~0.5TByte/sec in a system (assuming 40FPGAs). –80 PPC cores in a system.

POSITION 2 /hrs. Acceptance:  150mrad Beam:  -,1Gev/c Film: OPERA

BASE TRACKS ANGLE 2 /hrs. Acceptance:  150mrad Beam:  -,1Gev/c Film: OPERA

PH 2 /hrs. Acceptance:  150mrad Beam:  -,1Gev/c Film: OPERA