PED Roadmapping Issues Vijaykrishnan Narayanan Dept. of CSE Penn State University GSRC Workshop, March 20-21, 2003.

Slides:

Advertisements

Similar presentations

ITRS Roadmap Design + System Drivers Makuhari, December 2007 Worldwide Design ITWG Good morning. Here we present the work that the ITRS Design TWG has.

Advertisements

Subthreshold SRAM Designs for Cryptography Security Computations Adnan Gutub The Second International Conference on Software Engineering and Computer Systems.

Introduction to the TRAMS project objectives and results in Y1 Antonio Rubio, Ramon Canal UPC, Project coordinator CASTNESS’11 WORKSHOP ON TERACOMP FET.

Leakage Energy Management in Cache Hierarchies L. Li, I. Kadayif, Y-F. Tsai, N. Vijaykrishnan, M. Kandemir, M. J. Irwin, and A. Sivasubramaniam Penn State.

+ CS 325: CS Hardware and Software Organization and Architecture Internal Memory.

Microprocessor Reliability

1 Power Management for High- speed Digital Systems Tao Zhao Electrical and Computing Engineering University of Idaho.

Elettronica T A.A Digital Integrated Circuits © Prentice Hall 2003 Inverter CMOS INVERTER.

Design for Manufacturability and Power Estimation Lecture 25 Alessandra Nardi Thanks to Prof. Jan Rabaey and Prof. K. Keutzer.

CSE477 L19 Timing Issues; Datapaths.1Irwin&Vijay, PSU, 2002 CSE477 VLSI Digital Circuits Fall 2002 Lecture 19: Timing Issues; Introduction to Datapath.

SRAM Mohammad Sharifkhani. Effect of Mismatch.

abk Panel: PED/Reliability Roadmapping Issues u Question #1: More “issue-spotting” than questions s Runtime leakage vs. dynamic power s Impact.

Instrumentation: ground and noise Temperature Measurement.

OCIN Workshop Wrapup Bill Dally. Thanks To Funding –NSF - Timothy Pinkston, Federica Darema, Mike Foster –UC Discovery Program Organization –Jane Klickman,

Super-Drowsy Caches Single-V DD and Single-V T Super-Drowsy Techniques for Low- Leakage High-Performance Instruction Caches Nam Sung Kim, Krisztián Flautner,

University of Michigan Advanced Computer Architecture Lab. March 21, Key PED Challenges David Blaauw University of Michigan

04/11/02EECS 3121 Lecture 26: Interconnect Modeling, continued EECS 312 Reading: 8.2.2, (text) HW 8 is due now!

MICRO-MODEM RELIABILITY SOLUTION FOR NOC COMMUNICATIONS Arkadiy Morgenshtein, Evgeny Bolotin, Israel Cidon, Avinoam Kolodny, Ran Ginosar Technion – Israel.

Device Sizing Techniques for High Yield Minimum-Energy Subthreshold Circuits Dan Holcomb and Mervin John University of California, Berkeley EE241 Spring.

Penn ESE Spring DeHon 1 ESE (ESE534): Computer Organization Day 26: April 18, 2007 Et Cetera…

Chung-Kuan Cheng†, Andrew B. Kahng†‡,

On-Line Adjustable Buffering for Runtime Power Reduction Andrew B. Kahng Ψ Sherief Reda † Puneet Sharma Ψ Ψ University of California, San Diego † Brown.

CSE477 L26 System Power.1Irwin&Vijay, PSU, 2002 Low Power Design in Microarchitectures and Memories [Adapted from Mary Jane Irwin (

1 Drowsy Caches Simple Techniques for Reducing Leakage Power Krisztián Flautner Nam Sung Kim Steve Martin David Blaauw Trevor Mudge

VLSI System Design – ECES 681 Lecture: Interconnect -1 Prashant Bhadri Office: Rhodes Hall - 933C Department of ECECS, College of.

Power-Aware Computing 101 CS 771 – Optimizing Compilers Fall 2005 – Lecture 22.

Research Directions for On-chip Network Microarchitectures Luca Carloni, Steve Keckler, Robert Mullins, Vijay Narayanan, Steve Reinhardt, Michael Taylor.

Power, Energy and Delay Static CMOS is an attractive design style because of its good noise margins, ideal voltage transfer characteristics, full logic.

Digital Integrated Circuits© Prentice Hall 1995 Inverter THE INVERTERS.

1 A survey on Reconfigurable Computing for Signal Processing Applications Anne Pratoomtong Spring2002.

Unit 3a Industrial Control Systems

5/24/2016 Based on text by S. Mourad "Priciples of Electronic Systems" Digital Testing: Defects, Failures and Faults.

Juanjo Noguera Xilinx Research Labs Dublin, Ireland Ahmed Al-Wattar Irwin O. Irwin O. Kennedy Alcatel-Lucent Dublin, Ireland.

Advanced Computing and Information Systems laboratory Device Variability Impact on Logic Gate Failure Rates Erin Taylor and José Fortes Department of Electrical.

Year 2006 Report “Better” Managed and Controlled Transmission Grids using Advanced Technological Concepts Aty Edris EPRI Power Delivery & Markets

INTEGRATED CIRCUIT LOGIC FAMILY

9/27/2004EE 42 fall 2004 lecture 121 Lecture #12 Circuit models for Diodes, Power supplies Reading: Malvino chapter 3, Next: 4.10, 5.1, 5.8 Then.

Practical Reliability Engineering, Fifth Edition. Patrick D. T. O’Connor and Andre Kleyner. © 2012 John Wiley & Sons, Ltd. Chapter 9 Electronic Systems.

Chalmers University of Technology FlexSoC Seminar Series – Page 1 Power Estimation FlexSoc Seminar Series – Daniel Eckerbert

1 VLSI Design SMD154 LOW-POWER DESIGN Magnus Eriksson & Simon Olsson.

Roza Ghamari Bogazici University.  Current trends in transistor size, voltage, and clock frequency, future microprocessors will become increasingly susceptible.

Low-Power Wireless Sensor Networks

Logic Synthesis for Low Power(CHAPTER 6) 6.1 Introduction 6.2 Power Estimation Techniques 6.3 Power Minimization Techniques 6.4 Summary.

Gestionnaire du Réseau de Transport d 'Electricité 2008 IEEE PES General Meeting: Panel on Best Practices in State Estimation Experiences and practices.

Basics of Energy & Power Dissipation Lecture notes S. Yalamanchili, S. Mukhopadhyay. A. Chowdhary.

Washington State University

Statistical Sampling-Based Parametric Analysis of Power Grids Dr. Peng Li Presented by Xueqian Zhao EE5970 Seminar.

Network-on-Chip Energy-Efficient Design Techniques for Interconnects Suhail Basit.

Power Estimation and Optimization for SoC Design

Variation-Tolerant Circuits: Circuit Solutions and Techniques Jim Tschanz, Keith Bowman, and Vivek De Microprocessor Technology Lab Intel Corporation,

Variation. 2 Sources of Variation 1.Process (manufacturing) (physical) variations:  Uncertainty in the parameters of fabricated devices and interconnects.

Static WCET Analysis vs. Measurement: What is the Right Way to Assess Real-Time Task Timing? Worst Case Execution Time Prediction by Static Program Analysis.

By Nasir Mahmood.  The NoC solution brings a networking method to on-chip communication.

EE415 VLSI Design THE INVERTER [Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]

Penn ESE534 Spring DeHon 1 ESE534 Computer Organization Day 19: March 28, 2012 Minimizing Energy.

© PSU Variation Aware Placement in FPGAs Suresh Srinivasan and Vijaykrishnan Narayanan Pennsylvania State University, University Park.

Electrical Characteristics of Logic Gates Gate Characteristics Last Mod: January 2008  Paul R. Godin.

2/June/2009LHCb Upgrade1 Single ended ADC Differential ADC –Convert single ended signal to differential (use AD8138 amp) –ASIC differential output ADC.

Computer Architecture Chapter (5): Internal Memory

Proximity Optimization for Adaptive Circuit Design Ang Lu, Hao He, and Jiang Hu.

1 The user’s view  A user is a person employing the computer to do useful work  Examples of useful work include spreadsheets word processing developing.

National Conference on Recent Trends in Power Engineering

Reliability and Safety Analysis

Grid Integration of Intermittent Resources

BIC 10503: COMPUTER ARCHITECTURE

System Architecture for On-Chip Networks

Applications of GTX Y. Cao, X. Huang, A.B. Kahng, F. Koushanfar, H. Lu, S. Muddu, D. Stroobandt and D. Sylvester Abstract The GTX (GSRC Technology Extrapolation)

Presentation transcript:

PED Roadmapping Issues Vijaykrishnan Narayanan Dept. of CSE Penn State University GSRC Workshop, March 20-21, 2003

GSRC Panel ©. PSU 3/21/03 Why PED-Robustness Roadmap? 1970’s 1980’s 1990’s 2000’s area power speed/areaspeed low power speed/power speed/power/reliability reliable ultra-low power

GSRC Panel ©. PSU 3/21/03 Increasing variability Static u Changes in characteristics of devices and wire u Caused by the IC manufacturing process & wear-out. Runtime u Changes in V DD, temperature, V t, local coupling, external noise sources u Caused by runtime variation due to environment/operation.

GSRC Panel ©. PSU 3/21/03 Impact on Optimizations u Lack of modeling resources or information flow can transform variability to uncertainty. u Designing for worst case will not be power-efficient u Need for adaptation and dynamic monitoring s Enablers: Modeling of noise sources, Interaction of parameters that can be controlled at runtime, overheads

GSRC Panel ©. PSU 3/21/03 Power-Reliability Interaction u Supply voltage fluctuations can increase in power-aware design s Need models that can be adapted by architects/software designers that abstract detailed circuit issues s Cost of hardware solutions - supply grids, decoupling capacitances s Cost of software solutions – balancing work load u Substrate coupling between digital and analog u Interconnect reliability and power s Noise sources – single errors, multiple errors, amplitude of the error sources, modes of failure s Challenge – detecting the unobserved

GSRC Panel ©. PSU 3/21/03 Detectable & Residual Word Error Rate

GSRC Panel ©. PSU 3/21/03 Dynamic Switching Error Detection Codes

GSRC Panel ©. PSU 3/21/03 Power-Reliability Interaction u Supply voltage fluctuations can increase in power-aware design s Need models that can be adapted by architects/software designers that abstract detailed circuit issues s Cost of hardware solutions - supply grids, decoupling capacitances s Cost of software solutions – balancing work load u Substrate coupling between digital and analog u Interconnect reliability and power s Noise sources – single errors, multiple errors, amplitude of the error sources, modes of failure s Challenge – detecting the unobserved s How to offset encoding/decoding costs – Just Enough Power u Soft errors

GSRC Panel ©. PSU 3/21/03 Soft Errors in Leakage Controlled SRAMs u Q critical depends on capacitance and voltage and is the key parameter s Leakage controlled circuits are more susceptible to Soft errors u Support for error correction and detection (SECDED) s Specially important for dirty data not written back

GSRC Panel ©. PSU 3/21/03 Leakage Vs Soft Error Susceptibility

GSRC Panel ©. PSU 3/21/03 Conclusion u Need system approach that spans circuit, micro- architecture, software to addressing problems #1 Create models of physical/circuit effects reusable at higher levels of abstraction – what is important to optimize? #2 How to map applications onto the underlying heterogeneous fabrics to meet energy and reliability requirements? #3 What are new technologies that change slopes of technology trends? #4 Roadmap applications – what does the world need or rather what can we give the world?