1 Introduction VLSI Testing

2 Overview First digital products (mid 1940's) Complexity:low MTTF:hours Cost:high Present day products (mid 1980's) Complexity:high MTTF:Perhaps centuries? Cost: low

3 Observations  Testing is a cost burden, people buy digital devices to provide computation, control and/or communications.  The percentage of product development dollar allocated to testing continues to increase.  Test problems have changed, but the need for testing continues.  Test emphasis changes over time. As product cost declines, maintainability is less important than it once was.  There is no one single solution to the testing problem.

4 Focus  What makes circuits difficult to test (why do the algorithms fail)?  How can the complexity of the problem be reduced?  How can algorithms be made more effective?  What are the trade-offs between the various existing strategies?  What are the likely future directions?

5 DEFINITIONS Fault:a physical condition that causes a device, component, or element to fail to perform in required manner. Design Fault:a design characteristic of either hardware or software which causes or materially contributes to device malfunction independent of the presence of physical faults. Failure:the termination of the ability of a chip to perform its required function. Error:functional manifestation of a fault. Test Or Test Pattern:a specified primary input stimulus plus the expected fault-free primary output response. Fault Detection: application of test patterns which discover or are designed to discover the existence of faults.

6 DEFINITIONS (Continue) Fault Isolation: where a fault is known to exist, a test sequence which identifies or it is designed to identify the location of that fault within a specific circuit. Fault Coverage: An attribute of a test or test expressed as the percent of faults of the total fault population which that test procedure will detect. Fault Masking: The ability to avoid a fault by concurrently detecting and correcting all faults.

7 Failures are caused by defects such as: A.Contamination. B.Metallization Defects. C.Implant Defects D.Wafer Defects E.Oxide Defects F.Interconnect Defects G.Design Defects Such As: Too narrow conductors; high voltage drops. Too high voltage across oxide; hot electron injection. Too critical dimensions

8 FAILURES OBSERVED BY DIRECT INSPECTION OF 4-BIT MICROPROCESSOR CHIPS* SHORT BETWEEN METALLIZATIONS39% OPEN METALLIZATION14% SHORT BETWEEN DIFFUSIONS14% OPEN DIFFUSION6% SHORT BETWEEN METALLIZATION AND SUBSTRATE2% INOBSERVABLE10% MISCELLANEOUS15% * GALIAY, CROUZET, AND VERGNIAULT, IEEE TOC JUNE ALMOST ALL FAILURES ARE DUE TO SHORTS AND OPENS

9 MOS/CMOS has emerged as an important technology A WELL TESTED INTEGRATED CIRCUIT Is As IMPORTANT AS A WELL DESIGNED INTEGRATED CIRCUIT

10 COST A STANDARD AMONG PEOPLE FAMILIAR WITH THE TESTING PROCESS IS: If the cost for detecting a fault at the chip level is: $X Then to detect that same fault at the board level is: $10X At the system level: $100x At the system level but when it has to be found in the field: $1000X

11 Test Economics Shipped Product Quality Level Y-Process yield T-quality of test (fault coverage) Given the desired SPQL, and the process yield, the required test effectiveness, T, is fully determined. In logic circuits, T is computed by means of fault simulation. Defect level (DL) is often used as the measure of goodness, where: DL=1 –SPQL

12 MEAN FAULT CYCLE

13 SIGNIFICANCE OF FAULT MODELS A fault model is a hypothesis representing the fault mechanism in a circuit. The reliability of the product is determined by the accuracy and effectiveness of the fault model.

14 COMPLEXITY If a network contained N nets, any net may be good; s-a-1 or s-a-0. Thus all possible network state combinations would be 3 N. Assume a network with 100 nets, then there are 5x10 47 different combinations of faults. Test generation and fault simulation is approximately proportional to the number of gates to the power of 3. For functional testing if a network has N inputs (combinational) then 2 N patterns are required for complete functional test. If the network has N inputs and M latches then 2 N+M patterns are required. For VLSI assume N = 25 and M = 50 then #Patterns = 2 75  3.8×10 22 Assume test rate of 1 µ sec, then test time over 10 9 years

15 THE TESTING PROBLEM GIVEN A SET OF FAULLS, OBTAIN TEST VECTORS Q1: WHICH FAULTS? (FAULT MODELS) Q2: HOW IS TEST DERIVED? MANUALLY AUTOMATICALLY oALGORITHMS (ATG)-PODEM, SOFTG oKNOWLEDGE-BASED - HITEST Q3: HOW IS TEST QUALITY MEASURED? FAULT SIMULATION oCONCURRENT METHOD oFAULT SAMPLING FAULT COVERAGE AND PRODUCT_QUALITY

16 WHY MODEL FAULTS? I/O FUNCTION TESTS INADEQUATE FOR MANUFACTURING (FUNCTIONALITY vs. COMPONENT & INTERCONNECTION TESTING) FAULT MODEL IDENTIFIES TARGET FAULTS FAULT MODEL MAKES ANALYSIS POSSIBLE EFFECTIVENESS MEASURABLE BY EXPERIMENTS

17 SOME FAULT MODELS SINGLE STUCK FAULTS TRANSISTOR OPEN / SHORT FAULTS MEMORY FAULTS PLA FAULTS (STUCK, CROSS-POINT, BRIDG1NG) FUNCTIONAL (PROCESSOR) FAULTS DELAY FAULTS ANALOG FAULTS

18 SINGLE STUCK FAULTS ASSUMPTIONS: 1.ONLY ONE LINE IS FAULTY. 2.FAULTY LINE PERMANENTLY SET TO 0 OR 1. 3.FAULT CAN BE AT AN INPUT OR OUTPUT OF A GATE.

19 FAULT EQUIVALENCE TWO EQUIVALENT FAULTS ARE DETECTED BY EXACTLY THE SAME TESTS THREE FAULTS SHOWN ARE EQUIVALENT

20 EQUIVALENCE FAULT COLLAPSING N+2 FAULTS IN N-INPUT GATE

21 DOMINANCE FAULT COLLAPSING IF ANY TEST FOR F1 DETECTS F2 BUT CONVERSE IS NOT TRUE, THEN F2 DOMINATES F1. ONLY N+1 FAULTS IN N-INPUT GATE

22 The Sensitized Path Method Procedure: 1.Create a Sensitized Path from the fault to the primary output. 2.Justify the assignment of values to the outputs of internal gates. Example:

23 The Sensitized Path Method (Continue) Problems with the Sensitized Path Method 1.Making Choices 2.Reconvergent fan-out Paths Making Choices

24 The Sensitized Path Method (Continue) Reconvergent Fan-out Paths The sensitive path method is not guaranteed to find a test for a fault, even where such a test does exist. Example: Try to propagate through G5  Inconsistent Try to propagate through G6  Inconsistent It appears that there is no test for the fault. However, such a test does exist {0,0,0,0}

25 Redundancy and Undetectability Fault 3/1 is undetectable because the gate is redundant. Z = X1X2 + X1X2X3 = X1X2

26 The D-algorithm Example:

27 The D-algorithm Example: 0 1=D D 0 D 1 good 0 faulty

28 The D-algorithm Example:

29 The D-algorithm Example: D 0 D 1 0 × × D 1 good 0 faulty

30 The D-algorithm Example:

31 The D-algorithm Example: D D D 1 good 0 faulty