Asynchronous Input Example Program counter normally increments, jumps to address of interrupt subroutine on asynchronous interrupt How many states can Jump/Increment have? Interrupt Program Counter Jump Increment Clock F. U. Rosenberger, Washington University

Asynchronous Input Example – Revised Did we solve the problem? Why not? Interrupt Program Counter Jump Increment Clock F. U. Rosenberger, Washington University

Metastability Metastable State – signal not 1 or 0 or oscillating for a nondeterministic length of time Can occur when insufficient energy is applied to cause a latch to switch to either a 1 or 0. Examples: Dual processor with shared memory FIFO with asynchronous input and output Processor interrupts Yellow traffic light Two people meet in hallway Dog midway between two food dishes may starve Altera Application Note 42

Design Approach Where Metastability Present Don’t look for solution, there is none (don’t believe everything you read). Bottom line - Can’t guarantee correct operation with arbitrary clock and data phase Do design such that worst case probability of error is acceptable Do understand and be able to identify trouble spots in design F. U. Rosenberger, Washington University

Why Metastability is a “Special” Problem, Charles E. Molnar Because it “breaks most of the conceptual and computatonal tools that we use from day to day (e.g., binary or two state circuits) It defies careful and accurate measurements It can produce failures that leave no discernable evidence It can cause failures in systems whose software is “correct” and whose hardware passes all conventional tests It involves magnitudes of time and voltage to be removed from our daily experience F. U. Rosenberger, Washington University

Metastability in D Flip-Flops For D Flip-Flop, caused by setup or hold-time violations Altera Application Note 42 t MET = time of metastability

Analyzing Metastability Altera Application Note 42 Mean Time Between Failure (MTBF) for a synchronization flip-flop can be estimated with the following formula where f CLOCK is the system clock frequency f DATA is the data transfer frequency t MET is the additional time allowed for the flip-flop to settle C 1 and C 2 are device specific parameters found by plotting the natural log of MTBF versus t MET and performing linear regression analysis on the data

MTBF vs. T MET Altera Application Note 42 Time of metastability Mean Time Between Failure

Metastability Test Circuit Circuit that can be used to count metastable events Altera Application Note 42

Determining T MET for a given MTBF Altera Application Note 42 From test circuit we can find C 2 Then we can solve for C 1 With C 1 and C 2 known, can find required t MET for given clock and data rates and required MTBF.

Application Example Altera Application Note 42 Example Altera Flex 10K C 1 = 1.01 x , C 2 = x For one year (~3x10 7 seconds) and a data frequency of 2MHz and a clock frequency of 10 MHz Small increases in t MET dramatically affect the MTBF. A t MET delay to 1.59 ns increases MTBF to 10 years.

Synchronizer Circuits Example t MET is the clock period minus the setup time and wiring delays (and combinational logic delays if there is logic between the flip-flops). Data Clock Metastable Output Synchronized Output