CHAPTER 3 Digital Logic Structures Topics to be covered Logic gates Logic (Boolean) operations DeMorgan's Law Combinational logic circuits Truth tables and Boolean expressions Minimization of Boolean expressions Karnaugh maps Don’t care terms Sequential devices – Storage elements S. Barua – CPSC 240 sbarua@fullerton.edu http://sbarua.ecs.fullerton.edu

Logic Gates and Logic Operations Name Symbol Operation Input variable Output x y f(x,y) AND x 0 0 0 y f(x,y) = xy 0 1 0 1 0 0 1 1 1 The AND gate gives a logic 1 (high) output only when all the inputs are logic 1s. S. Barua – CPSC 240 sbarua@fullerton.edu http://sbarua.ecs.fullerton.edu

Logic Gates and Logic Operations Name Symbol Operation Input variable Output x y f(x,y) NAND x 0 0 1 f(x,y) = (xy)/ 0 1 1 y 1 0 1 1 1 0 The NAND gate is the complement of the AND gate. S. Barua – CPSC 240 sbarua@fullerton.edu http://sbarua.ecs.fullerton.edu

Logic Gates and Logic Operations Name Symbol Operation Input variable Output x y f(x,y) OR x 0 0 0 y f(x,y) = x+y 0 1 1 1 0 1 1 1 1 The OR gate gives a logic 0 (low) output only when all the inputs are logic 0. S. Barua – CPSC 240 sbarua@fullerton.edu http://sbarua.ecs.fullerton.edu

Logic Gates and Logic Operations Name Symbol Operation Input variable Output x y f(x,y) NOR x 0 0 1 y f(x,y) = (x+y)/ 0 1 0 1 0 0 1 1 0 The NOR gate is the complement of the OR gate. S. Barua – CPSC 240 sbarua@fullerton.edu http://sbarua.ecs.fullerton.edu

Logic Gates and Logic Operations Name Symbol Operation Input variable Output x f(x) Inverter x f(x) = x / 0 1 (NOT) 1 0 The inverter takes a single input and complements the input. S. Barua – CPSC 240 sbarua@fullerton.edu http://sbarua.ecs.fullerton.edu

Logic Gates and Logic Operations Name Symbol Operation Input variable Output x y f(x,y) XOR x 0 0 0 y f(x,y) = xy/ + x/y 0 1 1 1 0 1 1 1 0 The EXCLUSIVE-OR (XOR) gate gives a logic output of 1 when the input variables are different from each other. S. Barua – CPSC 240 sbarua@fullerton.edu http://sbarua.ecs.fullerton.edu

Logic Gates and Logic Operations Name Symbol Operation Input variable Output x y f(x,y) XNOR x 0 0 1 y 0 1 0 f(x,y) = xy + x/y/ 1 0 0 1 1 1 The EXCLUSIVE-NOR gate is the complement of the XOR gate. S. Barua – CPSC 240 sbarua@fullerton.edu http://sbarua.ecs.fullerton.edu

Truth Table Truth Table A tabular representation of the operations of logic gates or logic circuits Gives the relationship between the input and the output variables of a logic gate or a logic circuit S. Barua – CPSC 240 sbarua@fullerton.edu http://sbarua.ecs.fullerton.edu

DeMorgan's Law (A + B)/ = A/B/ (AB)/ = A/ + B/ S. Barua – CPSC 240 sbarua@fullerton.edu http://sbarua.ecs.fullerton.edu

Implementing a Boolean Expression Using Logic Gates Example: Implement the following Boolean function using appropriate logic gates f(A, B, C) = A/B + ABC/ + AB/C + A/C S. Barua – CPSC 240 sbarua@fullerton.edu http://sbarua.ecs.fullerton.edu

Definitions Product term: A series of Boolean variables that are related by the AND operator Example: xy, xyz Minterm: A product term that contains as many variables as there are in the function S. Barua – CPSC 240 sbarua@fullerton.edu http://sbarua.ecs.fullerton.edu

Characteristics of a Minterm (Product Term) In a minterm or a product term A regular variable has a value of logic 1 A complemented variable has a value of logic 0 Each minterm or a product term gives a value of 1 to the Boolean function. S. Barua – CPSC 240 sbarua@fullerton.edu http://sbarua.ecs.fullerton.edu

Example Consider a function with 3 input variables. All the possible input combinations and the corresponding minterms are as follows: Input combinations Minterms x y z   0 0 0 x/y/z/ 0 0 1 x/y/z 0 1 0 x/yz/ 0 1 1 x/yz 1 0 0 xy/z/ 1 0 1 xy/z 1 1 0 xyz/ 1 1 1 xyz S. Barua – CPSC 240 sbarua@fullerton.edu http://sbarua.ecs.fullerton.edu

Truth Table of a Boolean Function Truth table for a function with “n” input variables will contain: All the possible 2n combinations of the n input variables The corresponding values of the function for each input combination S. Barua – CPSC 240 sbarua@fullerton.edu http://sbarua.ecs.fullerton.edu

Truth Tables Example: For the logic function f(x,y,z) = x/y/z/ + xy/z + xyz (a) Derive the truth table x y z f(x,y,z) 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 S. Barua – CPSC 240 sbarua@fullerton.edu http://sbarua.ecs.fullerton.edu

Minimization of Boolean Functions Karnaugh Maps (K- Maps) Graphical representation of a logic function For an n-variable function, the K- Map consists of 2n cells The binary combination of each adjacent pair of cells in the K-Map differ from each other in only one bit position S. Barua – CPSC 240 sbarua@fullerton.edu http://sbarua.ecs.fullerton.edu

Karnaugh Maps (K- Maps) K-Map for a 2-variable K-Map for a 3-variable function function K-Map for a 4-variable function S. Barua – CPSC 240 sbarua@fullerton.edu http://sbarua.ecs.fullerton.edu

Minimizing Boolean Functions Minimization steps using K-Maps: Enter all the product terms (sum terms) of the given function on the K-Map Combine the adjacent cells on the map such that the cells are grouped in powers of 2 Try to maximize the number of cells combined because larger the number of cells grouped the fewer the number of variables in each term Get the reduced Boolean function by eliminating the variables that have changed their values inside a single block of grouped cells from the corresponding product (sum term) S. Barua – CPSC 240 sbarua@fullerton.edu http://sbarua.ecs.fullerton.edu

Example: Minimizing Boolean Functions Example: Minimize the Boolean function F(x,y,z) =  (2,3,4,5) S. Barua – CPSC 240 sbarua@fullerton.edu http://sbarua.ecs.fullerton.edu

Example: Minimizing Boolean Functions Example: Minimize the function F(w,x,y,z) =  (0,1,2,4,5,6,8,9,12,13,14) S. Barua – CPSC 240 sbarua@fullerton.edu http://sbarua.ecs.fullerton.edu

Don’t Care Conditions Sometimes a circuit is designed to respond to only some specific combinations of the input. The other combinations are not expected to be present in the circuit. The combinations of the input that are not expected in the circuit are called “don’t care terms” or “don’t care conditions.” Don’t care terms can be used to improve the minimization of a Boolean expression. S. Barua – CPSC 240 sbarua@fullerton.edu http://sbarua.ecs.fullerton.edu

Example: Don’t Care Conditions Example 1: Minimize F(A, B, C) = ABC + ABC +ABC Example 2: Minimize Example 1 by adding the “don’t care term” ABC to the function S. Barua – CPSC 240 sbarua@fullerton.edu http://sbarua.ecs.fullerton.edu

Combinational Circuit Versus Sequential Circuit The output of the circuit at any given time depends only on the inputs to the circuit at that time. Sequential Circuit Stores information The output of the circuit at any given time depends on both the inputs to the circuit at that time and the stored information. A sequential circuit has memory. S. Barua – CPSC 240 sbarua@fullerton.edu http://sbarua.ecs.fullerton.edu

Synchronous Circuits & Clock A sequential circuit whose operations are controlled by a clock is known as a synchronous circuit CLOCK Clock pulse Positive Negative width going edge going edge (Leading edge) (Trailing edge) Logic 1 Logic 0 Clock period Clock period (Clock cycle length or clock cycle time) S. Barua – CPSC 240 sbarua@fullerton.edu http://sbarua.ecs.fullerton.edu

Clock (Continued) Clock frequency: The number of times per second the clock makes the transition from logic low (0) to logic high (1). Measured in “Hz” (Hertz) which corresponds to “cycles per second”. If “f” is the clock frequency and “T” is the clock period, then f = 1/T The clock period is also called as the Clock cycle length or clock cycle time. Duty cycle: Percentage of time the clock remains on compared to the logic low region in clock period. If the clock remains on for 33% and remains off for 67% in a clock period, we say the clock has a duty cycle of 33%. S. Barua – CPSC 240 sbarua@fullerton.edu http://sbarua.ecs.fullerton.edu

Sequential Devices - Flip-flops The basic device used in the design of a sequential circuit is a flip-flop. We will look at the following four flip-flops: RS (Reset-set) flip-flop JK flip-flop D flip-flop T flip-flop S. Barua – CPSC 240 sbarua@fullerton.edu http://sbarua.ecs.fullerton.edu

RS flip-flop Symbol of a RS flip-flop Inputs: S & R S Q/ R Q Outputs: Q & Q/ S Q/ R Q Clock S. Barua – CPSC 240 sbarua@fullerton.edu http://sbarua.ecs.fullerton.edu

State Transition Table for an RS Flip-Flop Input Present State Next State S R Q Q/ Q Q/ 0 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 1 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1 0 1 d d 1 1 1 0 d d S. Barua – CPSC 240 sbarua@fullerton.edu http://sbarua.ecs.fullerton.edu

Switching Time & Propagation Delay The time for an individual element to change its state Propagation Delay: The time taken for the change to make its way through the whole circuit. S. Barua – CPSC 240 sbarua@fullerton.edu http://sbarua.ecs.fullerton.edu

Timing Diagram Example of a timing diagram for a RS flip-flop Assumptions: The flip-flop is triggered by the positive going edge of the clock The propagation delay is equal to the pulse width The initial value of Q is 1 S. Barua – CPSC 240 sbarua@fullerton.edu http://sbarua.ecs.fullerton.edu

JK Flip-flop Symbol of a JK flip-flop J Q/ K Q Inputs: J & K Outputs: Q & Q/ J Q/ K Q Clock S. Barua – CPSC 240 sbarua@fullerton.edu http://sbarua.ecs.fullerton.edu

State Transition Table for a JK Flip-Flop Input Present State Next State J K Q Q/ Q Q/ 0 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 1 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1 0 1 1 0 1 1 1 0 0 1 S. Barua – CPSC 240 sbarua@fullerton.edu http://sbarua.ecs.fullerton.edu

D flip-flop Symbol of a D flip-flop D Q/ Q Input: D Outputs: Q & Q/ Clock S. Barua – CPSC 240 sbarua@fullerton.edu http://sbarua.ecs.fullerton.edu

State Transition Table for a D flip-flop Input Present State Next State D Q Q/ Q Q/ 0 0 1 0 1 0 1 0 0 1 1 0 1 1 0 1 1 0 1 0 S. Barua – CPSC 240 sbarua@fullerton.edu http://sbarua.ecs.fullerton.edu

T Flip-flop Symbol of a T flip-flop T Q/ Q Input: T Outputs: Q & Q/ Clock S. Barua – CPSC 240 sbarua@fullerton.edu http://sbarua.ecs.fullerton.edu

State Transition Table for a T Flip-Flop Input Present State Next State T Q Q/ Q Q/ 0 0 1 0 1 0 1 0 1 0 1 0 1 1 0 1 1 0 0 1 S. Barua – CPSC 240 sbarua@fullerton.edu http://sbarua.ecs.fullerton.edu