Floorplanning Professor Lei He

Problem Formulation Given, for each block B i  Area of B i w i h i =A i  Aspect ratio of B i (continuous or discrete)  Connectivity Determine: for each block location (x i,y i ), and dimension (w i, h i ) min total area interconnections i i i i r h s  w

Slicing Floorplan and General Floorplan non-slicing floorplan Slicing Tree 1 2 h v h 74 v v 3h 65 Slicing floorplan

Overview of This Chapter  Module orientation problem  Slicing floorplan design  Non-slicing floorplan design  student presentation

Area Utilization  Area utilization  Depends on how nicely the rigid modules’ shapes are matched  Soft modules can take different shapes to “fill in” empty slots  Floorplan sizing m1 m7 m6 m5 m2 m4 m3 m1 m7 m6 m5 m2 m4 m3 m7 m1 m7 Area = 20x22 = 440Area = 20x19 = 380

Slicing Floorplan Sizing  Bottom-up process  Has to be done per floorplan perturbation  Requires O(n) time (N is the # of shapes of all modules) V LR H TB bibi aiai yjyj xjxj b i + y j max(a i, x j ) bibi aiai max(b i, y j ) a i + x j yjyj xjxj

Slicing Floorplan Sizing  Simple case: all modules are hard macros  No rotation allowed, one shape only 17x16 m1 9x15 m7 m6 9x7 m5 8x16 8x11 m2 m4 m3 4x x75x4 8x8 4x8 3x6 4x5 7x

Slicing Floorplan Sizing  General case: all modules are soft macros  Stockmeyer’s work (1983) for optimal module orientation  Non-slicing = NP complete  Slicing = polynomial time solvable with dynamic programming  Phase 1: bottom-up  Input: floorplan tree, modules shapes  Start with sorted shapes lists of modules  Perform Vertical_Node_Sizing & Horizontal_Node_Sizing  When get to the root node, we have a list of shapes. Select the one that is best in terms of area  Phase 2: top-down  Traverse the floorplan tree and set module locations

Sizing Example A A B B a1 a2 a3 4x6 5x56x4 b1 b2 b3 3x4 2x7 4x2 6x77x78x7 b1 a1 b1 a2 b1 a3 7x68x59x4 b2 a1 b2 a2 b2 a3 8x69x5 10x4 b3 a1 b3 a2 b3 a3

Stockmeyer Algorithm Procedure Vertical_Node_Sizing Input: Sorted lists L = {(a 1, b 1 ),..., (a s,b s )}, R = {(x 1, y 1 ),..., (x t, y t )}, where a i b j, x i y j (for all i < j) Output: A sorted list H = {(c 1, d 1 ),..., (c u,d u )}, where u ≤ s + t - 1, c i d j (for all i < j) Begin H := Ø i := 1, j := 1, k = 1 while (i ≤ s) and (j ≤ t) do (c k, d k ) := (a i + x j, max(b i, y j )) H := H U {(c k, d k )} k := k + 1 if max(b i, y j ) = b i then i := i + 1 if max(b i, y j ) = y j then j := j + 1

Complexity of the Algorithm n= # of leaves = 2 * # of modules d=depth of the tree Running time= O(nd) Storage = O(n) because, at depth k,  sum of the lengths of the lists =O(n)  time to construct these lists =O(n)  configurations stored at this node can be release as soon as the node is processed Extension Each module has k possible shapes Running time and storage O(nkd) depth k

Floorplan using Simulated Annealing References 1. D.F. Wong and C.L. Liu A New Algorithm for Floorplan Design 23rd IEEE/ACM Design Automation Conference 1986, P D.F. Wong and C.L. Liu Floorplan Design for Rectangular and L-shaped modules ICCAD-87 P D.F. Wong, H.W. Lceng, C.L. Liu Simulated Annealing for VLSI Design Kluwer Academic Publishers 1988 P31-71

Basic Ingredients for S.A.  Solution space  Neighborhood Structure  Cost Function  Annealing Schedule

Representation of Solutions      

Corresponding Slicing Tree May Not Unique      132+  4        Normalization: do not allow following slicing trees

Normalized Polish Expressions  2+  74+  # of operands = 4 # of operators = 2 …….. = 7 …….. = 5  Total length =2n-1  Permutation of { 1, 2, …, n} and # of operators =n-1  # of operators < # of operands at every position  No consecutive operators of the same type (due to normalization)

Neighborhood Structure The moves: M1: swap adjacent operands M2: Complement some chain of operators M3: swap 2 adjacent operand and operator Chain: +  +  +….. or  +  +  …  2+  74+  chains

Examples of Neighboring Solutions 1 2          +  1 2    M1 M3 M2

Cost Function  3   A ),(),( ),(    jicjidAA Eji ww  A=minimum area ij dc   w : W Wirelength:

Computing cost function  + +  7 4   ++  byax ii , b yax ii , a ybx ii , b yax ii , or b, yax ii ,Ayx ii  Ayx ii  a, ybx ii , Ayx ii  or

Computing Cost Function (Cont’d)  +  4  ++   108 9

Summary  Floorplan is a very important step for design planning  Floorplan may be performed before synthesis of each block (at RTL level)  Slicing floorplan allows efficient representation and optimization  Module orientation and sizing problem can be solved easily  Good results using SA on Polish expression representation  Recent progress  non-slicing floorplanning via Sequence pair representation  Floorplanning and system design co-optimization