Logic Synthesis 1 Outline –Logic Synthesis Problem –Logic Specification –Two-Level Logic Optimization Goal –Understand logic synthesis problem –Understand logic optimization problem

Logic Synthesis Problem Map from logic equations to gate-level combinational logic –will consider FSM synthesis later Goals –maximize speed –minimize power –minimize chip/board area Constraints –target technology –CAD tool CPU time a’bc + abc + dbc + d b c d b c d

Logic Specification.i 3.o 3.p 4 10x101 x x010.e Two-level logic equations –sum of products –“PLA format” –“ESPRESSO format” Multiple-level logic equations –Berkeley Logic Intermediate Format (BLIF) –arbitrary set of equations –generated in converting directly from RTL »e.g. logic equations for ALU –generated from gate-level netlist x = ab’ + b’c + abc’ y = abc’ + ab z = ab’ literaloperand x = abc’ + def + ghi + jkl +... y = bc + e’ + ghi + jk +... x = (a(b+c)d + ef(i+j))(k + l)

Logic Specification Logic equations are flattened to two levels –AND-OR, NAND-NAND, NOR-NOR –common starting point for most tools –eliminates any input bias –causes exponential explosion in equation size in worst case »does not occur in practice

Logic Synthesis Problem 1. logic equation simplification –reduce literal and operand count »less “stuff” to implement –generally reduces chip area –does not always minimize delay 2. logic synthesis –map equations to generic gates »AND, OR, NOT 3. gate-level optimization –“local” transformations for speed, area, power »e.g. AND-NOT => NAND –need estimate of technology costs 4. technology mapping –map from gates to component library »FPGAs, standard cells, TTL, etc.

Karnaugh Maps - Two-Level Minimization A B C D F = A’BC’D + A’BCD + ABC’D’ + ABC’D + ABCD + ABCD’ + AB’C’D’ + AB’C’D F = AB + AC’ + BD Build map - 2 N entries –label entries »0 - F = 0 »1 - F = 1 »X - F = don’t care Find minimum prime cover –cover - set of terms whose union is true for all entries that are 1 »can also cover all 0 entries instead and complement F –prime - terms are simplest (largest cover) they can be »AB vs. ABC + ABC’ –minimum - fewest terms F’ = A’B’ + B’C + A’D’

Examples A B C D F = AC’ + BD + ABCD’ ABCD’ is not prime A B C D F = AC’ + BD F is not a cover

Examples A B C D F’ = A’B’ + A’D’ + B’C A B C D 00 X X1 F = A + BD Use don’t care terms when determining if term is prime Solve for complement

Can Get Into Local Minima A B C D A B C D A B C D A B C D

Local Minima A B C D A B C D A B C D A B C D

A B C D Result is not minimal A B C D F = BD’ + A’D’ + A’B’F = A’B’ + BD’ Result is minimal Solution –try different cover sequences Minimum cover is NP-complete –exponential time in worst case Usually many minima

Problems with Karnaugh Maps Exponential space in number of inputs –e.g. 100 input function needs cells –very inefficient if number of 1 or 0 cells is small Needs of two-level minimization –efficient data structure »ideally linear in size of function –efficient means of searching for minimal prime cover »get close to optimal in reasonable time –serve as a building-block for multi-level minimization