Week 9b, Slide 1EECS42, Spring 2005Prof. White Week 9b OUTLINE Digital logic functions NMOS logic gates The CMOS inverter Reading Rabaey et al.: Section 5.2 Hambley: Sections (Logic)

Week 9b, Slide 2EECS42, Spring 2005Prof. White Digital Signals For a digital signal, the voltage must be within one of two ranges in order to be defined: Positive Logic: –“ low” voltage  logic state 0 –“high” voltage  logic state 1 “1” “0” V OH V IH V IL V OL undefined region increasing voltage V DD 0 Volts

Week 9b, Slide 3EECS42, Spring 2005Prof. White Logic Functions, Symbols, & Notation “NOT” F = A TRUTH NAME SYMBOL NOTATIONTABLE FA ABF “OR” F = A+B F A B AF ABF “AND” F = AB F A B

Week 9b, Slide 4EECS42, Spring 2005Prof. White “NOR” F = A+B ABF “NAND” F = A B F A B ABF “XOR” (exclusive OR) F = A + B F A B F A B ABF

Week 9b, Slide 5EECS42, Spring 2005Prof. White V DD /R D V DD NMOS Inverter (“NOT” Gate) v DS iDiD 0 v OUT v IN 0 Circuit: Voltage-Transfer Characteristic V DD VTVT AF A F increasing v GS = v IN > V T v GS = v in  V T v IN = V DD V DD

Week 9b, Slide 6EECS42, Spring 2005Prof. White Noise Margins Definition of Noise MarginsDefinition of Input Levels logic swing V sw V OH V OL Noise margin high Noise margin low

Week 9b, Slide 7EECS42, Spring 2005Prof. White NMOS NAND Gate Output is low only if both inputs are high V DD RDRD A B F ABF Truth Table

Week 9b, Slide 8EECS42, Spring 2005Prof. White NMOS NOR Gate Output is low if either input is high V DD RDRD AB F ABF Truth Table

Week 9b, Slide 9EECS42, Spring 2005Prof. White Disadvantages of NMOS Logic Gates Large values of R D are required in order to –achieve a low value of V OL –keep power consumption low  Large resistors are needed, but these take up a lot of space. One solution is to replace the resistor with an NMOSFET that is always on.

Week 9b, Slide 10EECS42, Spring 2005Prof. White The CMOS Inverter: Intuitive Perspective V DD RnRn V IN = V DD CIRCUIT SWITCH MODELS V DD RpRp V IN = 0 V V OUT V OL = 0 VV OH = V DD Low static power consumption, since one MOSFET is always off in steady state V DD V IN V OUT S D G G S D

Week 9b, Slide 11EECS42, Spring 2005Prof. White CMOS Inverter Voltage Transfer Characteristic V IN V OUT V DD 0 0 N: off P: lin N: lin P: off N: lin P: sat N: sat P: lin N: sat P: sat A BDE C

Week 9b, Slide 12EECS42, Spring 2005Prof. White N-Channel MOSFETP-Channel MOSFET

Week 9b, Slide 13EECS42, Spring 2005Prof. White CMOS Inverter Load-Line Analysis V OUT =V DSn I Dn =-I Dp 0 – V GSp =V IN -V DD + V IN = V DD + V GSp increasing V IN increasing V IN V IN = 0 V V IN = V DD V DD V OUT = V DD + V DSp V DSp = 0 V DSp = - V DD – V DSp =V OUT -V DD + 0

Week 9b, Slide 14EECS42, Spring 2005Prof. White V OUT =V DSn I Dn =-I Dp 0 V DD 0 CMOS Inverter Load-Line Analysis: Region A I Dn =-I Dp – V GSp =V IN -V DD + – V DSp =V OUT -V DD + V IN  V Tn

Week 9b, Slide 15EECS42, Spring 2005Prof. White V OUT =V DSn I Dn =-I Dp 0 V DD 0 CMOS Inverter Load-Line Analysis: Region B I Dn =-I Dp – V GSp =V IN -V DD + – V DSp =V OUT -V DD + V DD /2 > V IN > V Tn

Week 9b, Slide 16EECS42, Spring 2005Prof. White V OUT =V DSn I Dn =-I Dp 0 V DD 0 CMOS Inverter Load-Line Analysis: Region D I Dn =-I Dp – V GSp =V IN -V DD + – V DSp =V OUT -V DD + V DD – |V Tp | > V IN > V DD /2

Week 9b, Slide 17EECS42, Spring 2005Prof. White V OUT =V DSn I Dn =-I Dp 0 V DD 0 CMOS Inverter Load-Line Analysis: Region E I Dn =-I Dp – V GSp =V IN -V DD + – V DSp =V OUT -V DD + V IN > V DD – |V Tp |

Week 9b, Slide 18EECS42, Spring 2005Prof. White The CMOS Inverter: Current Flow during Switching V IN V OUT V DD V 0 0 N: off P:lin N:lin P: off N:lin P: sat N: sat P:lin N: sat P: sat A BDE C i i i S D G G S D V DD V OUT V IN