CMOS Detector Technology Markus Loose Rockwell Scientific Alan Hoffman Raytheon Vision Systems Vyshnavi Suntharalingam MIT Lincoln Laboratory Scientific Detector Workshop, Sicily 2005

Outline Markus Loose Alan Hoffman Vyshi Suntharalingam General Concept & Architecture Common Features of CMOS Sensors Stitching Technology Enables Large Arrays Monolithic CMOS Hybrid CMOS History of Hybrid CMOS ROIC Input Cells Detector Materials & Properties Low Noise Through Multiple Sampling CMOS Processing and General Limitations Emerging Technologies Vertical Integration Geiger-Mode Avalanche Photodiode Arrays Comparison: CMOS vs. CCD for Astronomy Markus Loose Alan Hoffman Vyshi Suntharalingam

Collection of High-Performance CMOS Detectors 3D stacked CMOS wafer sandbox HgCdTe 2K x 2K, 20 µm pixels InSb 2K x 2K, 25 µm pixels HgCdTe 4K x 4K mosaic, 18 µm pixels HgCdTe 2K x 2K, 18 µm pixels Monolithic CMOS 4K x 4K, 5 µm pixels

General CMOS Detector Concept CCD Approach CMOS Approach Pixel Charge generation & charge integration Charge generation, charge integration & charge-to-voltage conversion + Photodiode Amplifier Array Readout Charge transfer from pixel to pixel Multiplexing of pixel voltages: Successively connect amplifiers to common bus Sensor Output Output amplifier performs charge-to-voltage conversion Various options possible: no further circuitry (analog out) add. amplifiers (analog output) A/D conversion (digital output)

General Architecture of CMOS-Based Image Sensors Bias Generation & DACs (optional) Control & Timing Logic (opt.) Vertical Scanner for Row Selection Pixel Array A/D conversion (optional) Digital Output Horizontal Scanner / Column Buffers Analog Amplification Analog Output

Common CMOS Features CMOS sensors/multiplexers utilize the same process as modern microchips Many foundries available worldwide Cost efficient Latest processes available down to 0.13 µm CMOS process enables integration of many additional features Various pixel circuits from 3 transistors up to many 100 transistors per pixel Random pixel access, windowing, subsampling and binning Bias generation (DACs) Analog signal processing (e.g. CDS, programmable gain, noise filter) A/D conversion Logic (timing control, digital signal processing, etc.) Electronic shutter (snapshot, rolling shutter, non-destructive reads) No mechanical shutter required Low power consumption Radiation tolerant (by process and by design)

Special Scanning Techniques Supported by CMOS Different scanning methods are available to reduce the number of pixels being read: Allows for higher frame rate or lower pixel rate (reduction in noise) Can reduce power consumption due to reduced data Windowing Reading of one or multiple rectangular subwindows Used to achieve higher frame rates (e.g. AO, guiding) Subsampling Skipping of certain pixels/rows when reading the array Used to obtain higher frame rates on full-field images Random Read Random access (read or reset) of certain pixels Selective reset of saturated pixels Fast reads of selected pixels Binning* Combining several pixels into larger super pixels Used to achieve lower noise and higher frame rates * Binning is typically less efficient in CMOS than in CCDs.

Astronomy Application: Guiding Special windowing can be used to perform full-field science integration in parallel with fast window reads. Simultaneous guide operation and science data capture within the same detector. Two methods possible: Interleaved reading of full-field and window No scanning restrictions or crosstalk issues Overhead reduces full-field frame rate Parallel reading of full-field and window Requires additional output channel Parallel read may cause crosstalk or conflict No overhead  maintains maximum full-field frame rate Full field row Window Full field row Window

Electronic Shutter: Snapshot vs. Rolling Shutter Snapshot Shutter All rows are integrating at the same time. Typically more transistors per pixel and higher noise. Rolling Shutter (Ripple Read) Each row starts and stops integrating at a different time (progressively). Typically less transistors per pixel and lower noise. Row 1 integration time Row 1 integration time integr Row 2 integration time Row 2 integration time inte Row 3 integration time Row 3 integration time int Row 4 integration time Row 4 integration time i Row 5 integration time Row 5 integration time Read pixels of selected row Read pixels of selected row stop integrating start integrating stop integrating start integrating start 2nd integration if pixel supports “integrate while read”

Stitching Enables Large Sensor Arrays The small feature size of modern CMOS processes limits the maximum area that can be exposed in one step (so-called reticle) to about 22 mm. However, larger chips can produced by breaking up the design into smaller sub-blocks that fit into the reticle. Stitched CMOS Sensor Sub-blocks are exposed one after another Some blocks are used multiple times Ultimate limit is given by wafer size array horiscan1 horiscan2 V 3 2 1 Reticle array horiscan1 horiscan2 V 3 2 1 22mm

CMOS-Based Detector Systems Three possible CMOS Detector Electronics Configurations Detector Array Includes ADC, bias & clock generation Digital data Acquisition System Single Chip All electronics integrated in sensor chip Small, low system power Not always desirable (high design effort, glow) Detector Array Requires ext. ADC, bias and/or clock generation Analog output Bias Clocks ADC DAC Logic Memory Acquisition System Digital data Discrete Electronics Assembly of discrete chips and boards Large, higher power Reusable, modular, only PCB design required Analog output Bias Clocks ASIC Acquisition System Digital data Detector Array Requires ext. ADC, bias and/or clock generation Dual Chip All electronics integrated in a single companion chip Small, low system power Can be placed next to detector => low noise

Monolithic CMOS A monolithic CMOS image sensor combines the photodiode and the readout circuitry in one piece of silicon Photodiode and transistors share the area => less than 100% fill factor Small pixels and large arrays can be produced at low cost => consumer applications (digital cameras, cell phones, etc.) 3T Pixel Reset Select SF PD Read Bus photodiode transistors 4T Pixel Read Bus Select SF Pinned PD Reset p-sub n+ p+ TG

Complete Imaging Systems-on-a-Chip Monolithic CMOS technology has enabled highly integrated, complete imaging systems-on-a-chip: Single chip cameras for video and digital still photography Performance has significantly improved over last decade and is better or comparable to CCDs for many applications. Especially suited for high frame rate sensors (> Gigapixel/s) or other special features (windowing, high dynamic range, etc.) 2 Mpixel HDTV CMOS Sensor However, monolithic CMOS is still limited with respect to quantum efficiency: Photodiode is relatively shallow => low red response Metal and dielectric layers on top of the diode absorb or reflect light => low overall QE Backside illumination possible, but requires modification of CMOS process Quantum Efficiency of a CMOS sensor Si PIN NIR AR coating UV AR coating 3T pixel w/ microlenses photodiode Microlenses increase fill factor:

Outline Markus Loose Alan Hoffman Vyshi Suntharalingam General Concept & Architecture Common Features of CMOS Sensors Stitching Technology Enables Large Arrays Monolithic CMOS Hybrid CMOS History of Hybrid CMOS ROIC Input Cells Detector Materials & Properties Low Noise Through Multiple Sampling CMOS Processing and General Limitations Emerging Technologies Vertical Integration Geiger-Mode Avalanche Photodiode Arrays Comparison: CMOS vs. CCD for Astronomy Markus Loose Alan Hoffman Vyshi Suntharalingam

CMOS Processing Evolution for Hybrid Focal Planes Indium bump hybrid invented, circa 1975 1975 1980 1985 1990 1995 2000 2005 MOS w/surface channel CCD PMOS or NMOS CMOS CMOS ultimately "won" due to ease of design and availability of foundries

Silicon Readout Integrated Circuit (ROIC) Sensor Chip Assembly (SCA) Structure: Hybrid of Detector Array and ROIC Connected by Indium Bumps Detector Array Indium bump Detector Array Silicon Readout Integrated Circuit (ROIC) Mature interconnect technique: Over 4,000,000 indium bumps per SCA demonstrated 99.9% interconnect yield 16,000,000 Also called a Focal Plane Array (FPA) or Hybrid Array

CMOS SCA Revolution Large CMOS hybrids revolutionized infrared astronomy Growth in size has followed "Moore's Law" for over 20 years 18 month doubling time

Input Circuit Schematics Output S/F FET reset switch enable switch detector SFD input FET Cint DI load driver Cfb CTIA

Three Most Common Input Circuits for CMOS ROICs SFD (Source Follower per Detector) also called "Self Integrator" CTIA (Capacitance Transimpedance Amplifier) DI (Direct Injection) Advantages simple low noise low FET glow low power very linear gain determined by ROIC design (Cfb) detector bias remains constant large well capacity gain determined by ROIC design (Cint) Disadvantages gain fixed by detector and ROIC input capacitance detector bias changes during integration some nonlinearity more complex circuit FET glow higher power poor performance at low flux Comments Most common circuit in IR astronomy Very high gains demonstrated Standard circuit for high flux

Temperature and Wavelengths of High Performance Detector Materials Si:As IBC Si PIN InGaAs SWIR HgCdTe LWIR HgCdTe MWIR HgCdTe InSb Approximate detector temperatures for dark currents << 1 e-/sec

Detector Material Choices for CMOS Hybrid Arrays Si PIN InGaAs HgCdTe: 1.7m 2.5 m 5.2 m 10 m InSb Si:As IBC (BIB) Spectral Range*, m 0.4 – 1.0 0.9** – 1.7 0.9** – 2.5 0.9** – 5.2 5 – 10 0.4 – 5.2 5 – 28 Operating Temp***, K ~ 200 ~ 130 ~ 140 ~ 90 ~ 50 ~ 25? ~ 35 ~ 7 General Comments All detectors can have: 100% optical fill factor 100% internal QE (total QE depends on AR coat) Exception: Si:As is 40-70% between 5 and 10 m ROICs are interchangeable among detectors (except Si:As) HgCdTe and InGaAs require special packaging due to CTE mismatch between detector and ROIC * Long wave cutoff is defined as 50% QE point ** Spectral range can be extended into visible range by removing substrate *** Approximate detector temperatures for dark currents << 1 e-/sec

Noise in CMOS SCA/Hybrids Temporal White (uncorrelated) noise Reduced by multiple sampling 1/f (drift) noise Not a limiting factor in most astronomy focal planes Fixed pattern noise Caused by residual non-uniformity after calibration Can be reduced (eliminated?) by calibrating at multiple points in the dynamic range Random Telegraph Signal (RTS) Randomly occurring charge trapping/detrapping events Process, design and characterization dependent Personal experience: have not seen this

CMOS SCA Sampling Techniques Reset begins integration Voltage ramp for a single pixel Periodic sampling of detector signal possible during a long integration Two general methods of white noise reduction by multiple sampling Fowler sampling: average 1st N samples and last N samples; then subtract Sample up the ramp (SUTR): fit line (or polynomial) to all samples

Example of Noise vs Number of Fowler Samples 100 sec integrations in all cases Bare multiplexer 2 e- Data courtesy of Dr. Craig McMurtry, University of Rochester

Example of Fowler and SUTR Sampling in Uncorrelated (White) Noise Limit 6% difference Peak at Fowler N/3

Hybrid CMOS Summary CMOS ROIC Detectors SCAs Wide choice of processing foundries and analog circuits "System on a chip" is possible Clocks & biases A/D & DAC Any digital function Detectors Wide choice of detector materials Interchangeability among detectors and ROICs SCAs Up to 4K x 4K arrays successfully hybridized

Outline Markus Loose Alan Hoffman Vyshi Suntharalingam General Concept & Architecture Common Features of CMOS Sensors Stitching Technology Enables Large Arrays Monolithic CMOS Hybrid CMOS History of Hybrid CMOS ROIC Input Cells Detector Materials & Properties Low Noise Through Multiple Sampling CMOS Processing and General Limitations Emerging Technologies Vertical Integration Geiger-Mode Avalanche Photodiode Arrays Comparison: CMOS vs. CCD for Astronomy Markus Loose Alan Hoffman Vyshi Suntharalingam

Process Comparison CCD CMOS > 35 years of evolution “Trailing edge” fabs Economics of scale accelerate progress Lower fabrication cost, Foundry access High resistivity (deep depletion) substrates Controlled temperature ramps & stress control Epi doping optimized for digital CMOS Scalable to 300mm Buried channel Multiple oxidation cycles Complex implant engineering Rapid Thermal Processing (RTP) Single gate dielectric thickness Multiple gate dielectric thicknesses Doped polysilicon (single type) Complementarily doped polysilicon Silicided polysilicon and FET source/drain Highly nonplanar surfaces Conservative design rules Fine-line patterning Multiple metal layers (dense routing) Vulnerable to space-radiation-induced traps Highly suitable for long-term space-based applications 2mm 2mm 2mm Four-Poly OTCCD 180-nm SRAM cell Stacked via to poly

<0.25mm CMOS Technology Features Field Isolation LOCOS STI Voltage 3.3 - 5V 1.8 - 2.5V Gate Oxide 70 - 125A 32 - 50A Device Polycide/Poly Salicide Junction Profile Graded Junction Shallow Junction Planarization SOG and Reflow CMP Thermal Budget Furnace Anneal RTP Spacer Etch Oxide spacer SiN spacer Dielectric Material SiO2 SiO2/SiN/SiON This table compares technology elements for different gate-length nodes STI, salicides, RTP can generate and propagate crystalline defects, thus increasing dark current Composite dielectric materials degrade sensitivity and create interference effects which impact transmission, especially in the blue Silicide blocks are typically used for image sensor pixel regions Shallow junctions can be a problem for leakage

CMOS Pixel Process Flow Periphery CMOS Pixel Process Flow ONO spacer Poly STI Double S/D imp Oxide Deposit oxide Spin coat organic material Organic material Etch-back and remove oxide Photo resist Remove organic material Pattern oxide (photo/etch) Silicide is blocked from the photosensitive regions of the pixel Silicide Form silicide on peripheral devices Adapted from S. Wuu, TSMC

Cross Sectional TEM Photograph of Pixel Silicide gate Silicide blocks are incorporated at 0.15um and 0.13um technology nodes Lining oxide modifications are also made to manage stress According to TSMC, there are problems with manufacturing non-silicided regions at the 90-nm node. 0.3um 0.4um non-silicide S/D Courtesy S. Wuu, TSMC

Limitations of Standard Bulk CMOS APS Pixel Layout Fill factor tradeoff Photodetector and pixel transistors share same area PD from Drain-Substrate or Well-Substrate diode Low photoresponsivity Shallow, heavily doped junctions Limited depletion depth Absorption and reflection in poly, metal, and oxide layers Surface recombination at Si/SiO2 interface QE*FF > 60% is good, many < 20% High leakage LOCOS/STI, salicide Transistor short channel effects Substrate bounce and transient coupling effects RST ROW OUT VDD photodiode p-epi n-Well p-well Field Oxide VDD p+ ROW OUT n+ p+ Substrate RST Radiation effects Interface state generation especially in stressed locations Field inversion causing complete failure of the imager Layout-related mitigation techniques limit pixel fill factor

Advantages of Vertical Integration Conventional Monolithic APS 3-D Pixel Light PD pixel PD 3T Addressing pixel ROIC Processor Addressing A/D, CDS, … Pixel electronics and detectors share area Fill factor loss Co-optimized fabrication Control and support electronics placed outside of imaging area 100% fill factor detector Fabrication optimized by layer function Local image processing Power and noise management Scalable to large-area focal planes

Approaches to 3D Integration (To Scale) Tier-1 3D-Vias 3D-Vias 10 mm Tier-2 Slide showing “to scale” several different approaches to 3D circuit integration. Including (on the left) traditional bump bonds which are used to interconnect two circuit layers. (middle) A bulk-silicon-based through wafer via approach being pursued by several research organizations. (right) Lincoln’s approach based on SOI layer transfer. Note the much smaller size and 3-layer integration demonstrated by the MIT-LL approach. Lincoln’s approach : -- wafer scale - extendable to multiple layers (This slide previously cleared for ISSCC 2005 - slide #4) 10 mm 10 mm Photo Courtesy of RTI Bump Bond used to flip-chip interconnect two circuit layers Two-layer stack using Lincoln’s SOI-based vias Two-layer stack with insulated vias through thinned bulk Si

Four-Side Abuttable Goal 3-D CMOS imagers tiled for large-area focal planes Foundry fabricated daughter chip bump bonded to non-imaging side pixel Tile with Daughter Chip 8 mm Foundry Chip Overview physical description of this 3D stacked imager demonstration. (Elements of this slide were cleared for ISSCC 2005 - slide #7) Tiled Array mechanical mockup

Cross Sections Through 3-D Imager SOI-CMOS (Wafer 2) SEM cross section Photodiode (Wafer 1) 8 mm decorated Cross sectional SEM micrograph through functional active pixel imager. Each 8x8-um pixel contains three SOI-CMOS transistors in Tier-2 and one 3-D via to contact the Tier-1 photodiode. (This slide previously cleared for this meeting) Transistor CMOS Vias 3D-Via Bond Interface Diode Pixel 5 mm

Four-Side Abuttable Vertically Integrated Imaging Tile Wafer-Scale 3D circuit stacking technology Silicon photodetector tier SOI-CMOS address and readout tier Per-pixel 3D interconnections 1024x1024 array of 8mmx8mm pixels 100% fill factor >1 million vertical interconnections per imager Front Illuminated Back Illuminated The largest-area imager we have built using our 3-D stacking technology was this 1024x1024 pixel imager described here. The vertical integration permitted very small (8umx8um) pixels with a vertical interconnection in every pixel The device has been successfully processed for backside illumination and continues to operate as an image sensor. (This slide previously cleared for ISSCC 2005 as slides #7 and #33) Presented at 2005 ISSCC

Geiger-Mode Imager: Photon-to-Digital Conversion Digitally encoded photon flight time Pixel circuit Digital timing circuit photon APD/CMOS array APD Lenslet array Focal-plane concept Quantum-limited sensitivity Noiseless readout Photon counting or timing

3-D Laser Radar Sensor Development Objective: single flash, non-scanned 3D area imager Pixel stores range, not intensity, information 3-D imaging provides Robust object recognition relatively independent of lighting, reflectivity Separates objects behind foliage, camouflage 3-D Brassboard image Active intensity image SUV behind camouflage SUV Npe= 105 3-D images enable easy image segmentation based on range, object recognition signatures that are robust to lighting or reflectivity variations, and object recognition through camoflage. 3D images can also be used to align intensity images from multiple sensors in different locations. Here is an example comparing an intensity image of two vehicles with a 3-D image of the same scene. One vehicle is obscured by a camoflage net. The 3-D image, when rotated using rendering software, reveals the camoflaged vehicle clearly. It is not possible to make out the camoflaged vehicle at all in the intensity image, even with over 250 times as many photoelectrons per pixel.

Technology Development Evolution Discrete 4x4 arrays 4x4 arrays wire bonded to 16-channel CMOS readout 32x32 arrays fully integrated with 32x32 CMOS readout APD’s 1996 This chart summarizes the development of these sensors over the past 5 years. -we developed our own design of a silicon APD, ans are currently developing sensors for 1.06 and 1.55 micron wavelength radiation. -The early brassboard system which produced the images shown on the last slide used an external readout circuit. -We next productd an integrated 4x4 array which had integrated CMOS readout circuits and wire bonded the small APD array to it. -Last year I reported on first operation of a 32x32 pixel APD array integrated with a CMOS readout circuit with one circuit for each pixel. Work this year has focused on improving this first circuit. 2001

3D Laser Radar Focal Plane (3D)2 Laser radar focal plane based on single-photon-sensitive Geiger-mode avalanche photodiodes 64 x 64 demonstration circuit (scalable) Pixel size reduction from 100 mm to 30 mm Timing resolution reduction from 1 ns to 0.1 ns 100x reduction in voxel volume APD Tier-1: Avalanche Photodiode Tier-2: 3.3V FDSOI CMOS Tier-3: 1.5V FDSOI CMOS Pseudorandom counter circuit Avalanche PD APD drive/sense circuit VISA APD Pixel Circuit (~250 transistors/pixel) 3D-Integrated Tier-1/Tier-2 wafer pair electrical test vehicle Third application area, a 3-tier Geiger-mode avalanche photodiode (APD) 3D LIDAR array, using an APD tier, a 3.3 volt CMOS tier, and a 1.5 volt CMOS tier. 150 mm

Outline Markus Loose Alan Hoffman Vyshi Suntharalingam General Concept & Architecture Common Features of CMOS Sensors Stitching Technology Enables Large Arrays Monolithic CMOS Hybrid CMOS History of Hybrid CMOS ROIC Input Cells Detector Materials & Properties Low Noise Through Multiple Sampling CMOS Processing and General Limitations Emerging Technologies Vertical Integration Geiger-Mode Avalanche Photodiode Arrays Comparison: CMOS vs. CCD for Astronomy Markus Loose Alan Hoffman Vyshi Suntharalingam

Comparison CMOS vs. CCD for Astronomy Property CCD Hybrid CMOS Resolution > 4k x 4k 2k x 2k in use, 4k x 4k demonstrated Pixel pitch 10 – 20 µm 18 – 40 µm, < 10 µm demonstrated Typ. wavelength coverage 400 – 1000 nm 400 – 1000 nm with Si PIN 400 – 5000 nm with InSb or HgCdTe Noise Few electrons Few electrons with multiple sampling Shutter Mechanical Electronic, rolling shutter Power Consumption High Typ. 10x lower than CCD Radiation Sensitive Much less susceptible to radiation Control Electronics High voltage clocks, at least 2 chips needed Low voltage only, can be integrated into single chip Special Modes Orthogonal Transfer, Binning, Adaptive Optics Windowing, Guide Mode, Random Access, Reference Pixels, Large dynamic range (up the ramp) Silicon PIN hybrid detectors have become a serious alternative to CCDs providing a number of significant advantages, specifically for large mosaic focal plane arrays.

Conclusion CCD It’s happening! Transition CMOS