Exploiting Symmetry in SAT-Based Boolean Matching for Heterogeneous FPGA Technology Mapping Yu Hu 1, Victor Shih 2, Rupak Majumdar 2 and Lei He 1 1 Electrical Engineering Dept., UCLA 2 Computer Science Dept., UCLA Presented by Yu Hu Address comments to

Outline Background and Motivations Review of Standard SAT-based Boolean Matching Proposed Improvements Experimental Results Conclusion and Future Work

Background FPGA technology mapping  Map a design into a network of Programmable Logic Blocks (PLBs)  Optimize for area, speed and/or power PLB containing heterogeneous devices requires Boolean matching (BM) to determine whether function f can be implemented by hardware component H

Example: Boolean Matching (BM) for PLB Answer a Yes-No question  Can a Boolean function f be implemented in PLB p?  If yes, give the configuration bits of LUTs. f1 = e*a + c*a + d*a + b*a f2 = a + b + c + d + e f1 = (e + c + d + b)*a i.e., f1 = z*a z = e + c + d + b z e c d b a f1 L0 (0000)0 L1 (0001)1 L2 (0010)1 ……… L15(1111)1

Motivation for SAT Based PLB BM Application of FPGA PLB Boolean matching  Technology mapping  Re-synthesis Existing BM algorithms  Decomposition based BM is lack of flexibility, i.e., algorithm is only applicable to selected BLE structure [Cong, TCAD’01]  BDD based BM is not scalable (memory explosion) [Ciric, TCAD’03]  Fast BM is hard to deal with programmable devices [Wei, ISQED’06] SAT based BM [Ling, DAC’05][Safarpour, DAC’06][Cong, FPGA’07]  Introduces extreme flexibility  Provide a tradeoff between memory and runtime to deal with complicated BLE structures  Still slow, hard to be applied to complex PLBs

Review: SAT Based Encoding for BM Encoding non-programmable devices  Requires common/interconnect variables  Is a linear time procedure Example: f AND = (x 2 +¬z 1 ) (x 1 +¬z 1 ) (¬x 2 +¬x 1 + z 1 ) f OR = (¬x 3 +g) (¬z 1 +g) (x 3 +z 1 + ¬g) f total = f AND f OR = (x 2 +¬z 1 ) (x 1 +¬z 1 ) (¬x 2 +¬x 1 + z 1 ) (¬x 3 +g) (¬z 1 +g) (x 3 +z 1 + ¬g)

Review: SAT Based Encoding for BM Encoding programmable devices  Configuration bits are encoded f LUT =( x 1 + x 2 + ¬L 0 + z 1 ) ( x 1 + x 2 + L 0 + ¬ z 1 ) ( x 1 + ¬ x 2 + ¬L 1 + z 1 ) ( x 1 + ¬ x 2 + L 1 + ¬ z 1 ) (¬ x 1 + x 2 + ¬L 2 + z 1 ) (¬ x 1 + x 2 + L 2 + ¬ z 1 ) (¬ x 1 + ¬ x 2 + ¬L 3 + z 1 ) (¬ x 1 + ¬ x 2 + L 3 + ¬ z 1 )

Review: SAT Based Encoding for BM G LUT2 =( x 1 + x 2 + ¬L 0 + z) ( x 1 + x 2 + L 0 + ¬ z) ( x 1 + ¬ x 2 + ¬L 1 + z) ( x 1 + ¬ x 2 + L 1 + ¬ z) (¬ x 1 + x 2 + ¬L 2 + z) (¬ x 1 + x 2 + L 2 + ¬ z) (¬ x 1 + ¬ x 2 + ¬L 3 + z) (¬ x 1 + ¬ x 2 + L 3 + ¬ z) G AND2 = ( x 3 + ¬f ) (¬ x 3 + ¬f ) ( ¬x 3 + ¬z + f ) G = G AND2 · G LUT2 x1x2x3x1x2x3 f SAT: G expand = G[X/000, f/0, z/z 0 ] · G[X/001, f/0, z/z 1 ] G[X/010, f/1, z/z 2 ] · G[X/011, f/0, z/z 3 ] G[X/100, f/1, z/z 4 ] · G[X/101, f/1, z/z 5 ] G[X/110, f/1, z/z 6 ] · G[X/111, f/1, z/z 7 ] Boolean function The solution of this SAT problem corresponds to the Boolean matching results Configuration bits are encoded as SAT literals

Handle Input Permutation and Bridge Virtual MUXes increase runtime exponentially!

Impact of Virtual MUXes

Symmetries in Circuits and PLB Functional Symmetries  Variable a and variable b are symmetric if swapping a and b does not change the truth table of function F(…,a,…,b,…)  General symmetries which consider the permutation of more than two variables can also be explored  Eg: F(a,b,c) = a(b+c), where b and c are symmetric Architectural Symmetries  Structures of certain inputs of a PLB are equivalent  Eg: Inputs of the primary input LUTs of each PLB are symmetric F(a, b, c, d) F(b, a, c, d)

Impact of Considering Symmetries The number of distinct permutations under symmetries decreases substantially  Functional symmetries and architecture symmetries independently reduce 100x permutations

Overall Algorithm Target architecture Pre-calculate architecture symmetries patterns Architecture symmetry information Characteristic function template Generate characteristic function template Boolean function Functional symmetry detection Pruning by architecture symmetries Non-redundant permutation set (NPS) Is NPs empty? Pre-process for the target PLB, one-time cost Exit Pop a permutation p Y N

Overall Algorithm (cont.) Replicate CNFs of p Solve the SAT problem SAT ? Return implementable Target architecture Pre-calculate architecture symmetries patterns Architecture symmetry information Characteristic function template Generate characteristic function template Pre-process for the target PLB, one-time cost Exit Y Is NPs empty? Pop a permutation p Y N N

Experimental Results Experimental settings  Tested by Boolean functions in MCNC circuits  Target PLB is “ PLB_d ”  Use “ minSAT1.14 ” to solve SAT instances Obtain over 100x speedup compared to the standard approach [Ling ’ 05] Breakdown of speedup techniques

Conclusions and Future Work An improvement for SAT-based Boolean matching is presented by considering functional and architectural symmetries Over 100x speedup is obtained compared to the standard SAT-based Boolean matching approach Future Work  Integrate the improved SAT-based Boolean matcher into heterogeneous FPGA technology mapping phase  Perform architecture exploration by our improved technology mapper

Thank You! Exploiting Symmetry in SAT-Based Boolean Matching for Heterogeneous FPGA Technology Mapping Yu Hu, Victor Shih, Rupak Majumdar and Lei He