1. Address comments to lhe@ee.ucla.edu Robust FPGA Resynthesis Based on Fault-Tolerant Boolean Matching Yu Hu 1, Zhe Feng 1, Lei He 1 and Rupak Majumdar 2 1 Electrical Engineering Dept., UCLA 2 Computer Science Dept., UCLA Presented by Yu Hu

2. Outline Background and Motivation Preliminaries Robust Resynthesis Algorithms Experimental Results Conclusion and Future Work

3. Background Late CMOS scaling reduces device reliability Single event upset (SEU) due to cosmic rays  Affects configuration SRAM cells in FPGAs Permanent soft error rate (SER) Need rewriting SRAM for recovery  Affects combinational circuits and FFs Transient SER Can be recovered in multiple clock cycles

4. Fault Tolerance Techniques for FPGAs

5. Our work Low-cost, complementary approach to existing techniques! [A. Djupdal and P. Haddow, Yield Enhancing Defect Tolerance Techniques for FPGAs, MAPLD 2006]

6. Stochastic Synthesis and Logic Masking Stochastic synthesis assumes probabilistic logic values to model effect of random defects  Break the conventional Boolean view which assumes deterministic Boolean ‘0’ and ‘1’ values Key to stochastic synthesis: Logic Masking Masked faults 0 1

7. Stochastic Synthesis and Logic Masking (cont.) Stochastic Synthesis intelligently places logic masking. Logic Masking reduces the probability of the propagation of random faults  Maximizes the stochastic yield However, logic synthesis to maximize yield rate w/o explicit redundancy and testing has not been studied for fault tolerance! Key questions  How much does logic masking affect robustness?  How and where to place logic masking?

8. How much Logic Masking Affect Robustness? 18 synthesis solutions obtained by Berkeley ABC (for MCNC i10, LUT bit fault rate = 0.1%) Different synthesis leads to different logic masking. Stochastic synthesis maximizes logic masking!

9. How and Where to Place Logic Masking? — Our Major Contributions Propose a Robust FPGA resynthesis (ROSE)  Maximize the stochastic yield rate for FPGAs  No need to locate faults  Use the same synthesis for different chips of one FPGA application Proposed a new PLB template for robustness ROSE + Robust Template reduces fault rate by 25% with 1% fewer LUTs, and increases MTBF by 31% while preserving the logic depth  compared to Berkeley ABC

10. Outline Background Preliminaries Robust Resynthesis Experimental Results Conclusion and Future Work

11. FPGA Synthesis Flow Attempt to re-map a logic block by Boolean matching Boolean matching can be used to handle both homogenous and heterogeneous PLBs

12. FPGA Synthesis Flow (cont.) Multi-iterations of Boolean Matching-based Resynthesis (Source: Andrew Ling, University of Toronto, DAC'05)

13. Boolean Matching for Resynthesis 2-LUT fg ? Formulate the sub-problem of resynthesis to Boolean matching (BM)  BM: Can function f be implemented in circuit g ?  Resynthesis: Is there a configuration to g so that for all inputs to g, f is equivalent to g ? Existing algorithms: area/delay-optimal (Source: Andrew Ling, University of Toronto, DAC'05)

14. Outline Background Preliminaries Robust Resynthesis  Problem Formulation  FTBM Algorithm  Robust PLB Template Experimental Results Conclusion and Future Work

15. Modeling of Faults Model both faults in LUT configurations and the faults in intermediate wires as random variables, whose probabilities are given as inputs of our problem.

16. ROSE: Robust Resynthesis w/ FTBM Boolean Matching  Inputs PLB H and Boolean function F Fault rates for the inputs and the SRAM bits of the PLB  Outputs Either that F cannot be implemented by PLB H Or the configuration of H which minimizes the probability that the faults are observable in the output of the PLB under all input vectors.  FTBM tasks breakdown: Step 1: Find a Boolean matching solution Step 2: Evaluation the stochastic fault rate of a solution Fault-Tolerant Boolean Matching

17. FTBM Step1: SAT Encoding for FTBM If implementable, multiple configurations might exist The one with minimal fault rate is needed! Conjunctive Normal Form (CNF)

18. Deterministic SAT vs. SSAT FTBM Step2: Fault Rate Calculation Based on SSAT Deterministic SAT Stochastic SAT Simulation-based fault rate calculation  Not scalable for multiple defects SAT-based fault rate calculation  Intelligently modeling random defects

19. GUI Version 1 SSAT Encoding for Fault Rate Calculation Faults in intermediate wires Faults in LUT configurations Binary search is performed to find the maximal β

20. Example: SAT-Based FTBM abcg 0001 0011 0101 0110 1001 1011 1100 1110 g= ! x 1 ! x 3 + ! x 2 Boolean function PLB Template Boolean matching

21. Example: SAT-Based FTBM Step1: CNFs for the PLB template G LUT = ( x 1 + x 2 + ¬L 0 + z) ( x 1 + x 2 + L 0 + ¬ z) ( x 1 + ¬ x 2 + ¬L 1 + z) ( x 1 + ¬ x 2 + L 1 + ¬ z) (¬ x 1 + x 2 + ¬L 2 + z) (¬ x 1 + x 2 + L 2 + ¬ z) (¬ x 1 + ¬ x 2 + ¬L 3 + z) (¬ x 1 + ¬ x 2 + L 3 + ¬ z) PLB Characteristic Function: G = G LUT1 · G LUT2 · G LUT3

22. Example: SAT-Based FTBM Step2: Replication based on Truth Table abcg 0001 0011 0101 0110 1001 1011 1100 1110 SAT Instance: G expand = G[X/000, f/1, z/z 0 ] · G[X/001, f/1, z/z 1 ] G[X/010, f/1, z/z 2 ] · G[X/011, f/0, z/z 3 ] G[X/100, f/1, z/z 4 ] · G[X/101, f/1, z/z 5 ] G[X/110, f/0, z/z 6 ] · G[X/111, f/0, z/z 7 ] G = G LUT1 · G LUT2 · G LUT3 Replication

23. Example: SAT-Based FTBM Step3: SAT Solving and Mapping SAT Instance: G expand = G[X/000, f/1, z/z 0 ] · G[X/001, f/1, z/z 1 ] G[X/010, f/1, z/z 2 ] · G[X/011, f/0, z/z 3 ] G[X/100, f/1, z/z 4 ] · G[X/101, f/1, z/z 5 ] G[X/110, f/0, z/z 6 ] · G[X/111, f/0, z/z 7 ] SAT! Returned SAT assignments: L1(00) = 0, L1(01)=0, L1(10)=0, L1(11)=1, …

24. Example: SAT-Based FTBM Step4: Exploring More SAT Solutions Augmented SAT Instance: G expand = G[X/000, f/1, z/z 0 ] · G[X/001, f/1, z/z 1 ] G[X/010, f/1, z/z 2 ] · G[X/011, f/0, z/z 3 ] G[X/100, f/1, z/z 4 ] · G[X/101, f/1, z/z 5 ] G[X/110, f/0, z/z 6 ] · G[X/111, f/0, z/z 7 ] ¬ (L1(00) = 0, L1(01)=0, L1(10)=0, L1(11)=1, …) /* Complement of previous SAT assignments */ New ConfigurationPrevious Configuration Fault rate = 0.2 Fault rate = 0.3

25. PLB Templates for SAT-based Resynthesis Area efficient templates [A. Ling, DAC’05] Proposed robust template w/ path-reconvergence  Can be configured by existing FPGAs

26. Templates for SAT-based Resynthesis (cont.) Robust PLB template introduces more potential of don’t-cares ROSE maximizes don’t-cares iteratively at each template output Satisfiability don’t-care Observability don’t-care

27. Outline Background Preliminaries Robust Resynthesis Experimental Results Conclusion and Future Work

28. Experimental Settings Implementation in OAGear  SAT-BM uses miniSAT2.0 QUIP benchmarks are tested  Are first mapped with 4-LUTs by Berkeley ABC Resynthesis settings  One traversal is performed  Blocks with up to 10 inputs are considered The fault rate of the chip is calculated by Monte Carlo simulation with 20K random vectors assuming the single fault Results are verified by ABC equivalency checkers

29. Full-chip Fault Rate by Monte Carlo Simulation >30% fault rate reduction! Fault rate is the percentage of input vectors that cause observable output errors assuming the single fault.

30. Area (LUT#) ABC vs. ROSE/A vs. ROSE/R: 1: 0.9 : 0.99 ABC vs. ROSE/A vs. ROSE/R: 1: 0.9 : 0.99

31. Estimation of Mean Time Between Failure SER modeling: [Mukherjee, HPCA, 2005] Assume max-size FPGA: 330,000 LUTs 31% MTBF increase!

32. Outline Background Preliminaries Robust Resynthesis Experimental Results Conclusion and Future Work

33. Conclusions and Future Work Developed ROSE and a robust template.  ROSE is an orthogonal approach compared to existing fault-tolerant technique.  Virtually no overhead on power, delay and area In the future, we will consider  Multiple correlated faults,  Alternative algorithms,  Extension to standard cell-based circuits,  Impacts on testability.

34. Robust FPGA Resynthesis Based on Fault-Tolerant Boolean Matching Yu Hu, Zhe Feng, Rupak Majumdar and Lei He University of California, Los Angeles

35. Backup Slides

36. Fault Characteristics of Templates — Estimated Based on Boolean Functions The minimal achievable fault rate The fault gap of template  FTMB+ (min fault rate) vs. FTMB- (max fault rate)  Fault gap = Max fault rate - Min fault rate

37. Fault Characteristics of Templates (cont.) — Estimated Based on Boolean Functions The minimal fault rates achievable by R-PLB are generally less than those achievable by A-PLB2. The fault gap of template R-PLB is generally wider than that of template A-PLB2  There exists more flexibility to place don't-cares in R-PLB.

38. Runtime Resynth vs. ROSE/A vs. ROSE/R: 1: 3 : 10 Resynth vs. ROSE/A vs. ROSE/R: 1: 3 : 10

39. Background Late CMOS scaling reduces device reliability and increases both permanent and transient defects Major fault tolerance techniques for PLDs:  Triple Modular Redundancy (TMR)  Manufacturer-masking  Chip-wise Synthesis  Precompiled Multiple Configurations

40. Background Late CMOS scaling reduces device reliability and increases both permanent and transient defects Existing tolerance techniques for PLDs:  Triple Modular Redundancy (TMR)  Manufacturer-masking  Chip-wise Synthesis  Precompiled Multiple Configurations However, logic synthesis to maximize yield rate w/o explicit redundancy and w/o testing has not been studied for fault tolerance!

41. Motivation Example1: Boolean Matching vs. Fault Tolerance g = !b + !a*!c, mapped by 2-LUTs (Courtesy: K. Patel et al, “Evaluating Circuit Reliability Under Probabilistic Gate-Level Fault Models”, IWLS’03) >20% difference! 1 1 Masked faults 0 1

42. How does Logic Masking affact Robustness? Logic masking in Boolean Matching g = !b + !a*!c, mapped by 2-LUTs (Courtesy: K. Patel et al, “Evaluating Circuit Reliability Under Probabilistic Gate-Level Fault Models”, IWLS’03) >20% difference! Masked faults 0 1 0

43. Full-chip Fault Tolerance ROSE/A: ROSE with A-PLB* ROSE/R: ROSE with R-PLB [8]: deterministic SAT-based resynthesis for area reduction

44. Problem Formulation – FTBM Inputs  PLB H and Boolean function F  Fault rates for the inputs and the SRAM bits of the PLB Outputs  Either that F cannot be implemented by PLB H  Or the configuration of H which minimizes the probability that the faults are observable in the output of the PLB under all input vectors.

45. Fault Characteristics of Templates — Estimated Based on Full-chip 5x difference!

46. Estimation of Mean Time Between Failure Source: [Mukherjee, HPCA, 2005], 330,000 LUTs Assumptions  MTBF = 10 9 /(24x365) FIT total  FIT total = C x Vulnerability Rate x Intrinsic Error Rate  Intrinsic Error Rate = Area x FIT rate  Vulnerability Rate = Mean of fault rate  FIT rate = 0.01 FIT/bit, C = 100 31% MTBF increase!