1. FPGA PLB Evaluation using Quantified Boolean Satisfiability Andrew C. Ling M.A.Sc. Candidate University of Toronto Deshanand P. Singh Ph.D. Altera Corporation Professor Stephen D. Brown Altera Corporation Toronto University of Toronto

2. Background: FPGA

3. Background: K-LUT

4. Background: K-Input PLB The 3-input PLB below CANNOT implement any arbitrary 3-input function The 3-input PLB below CANNOT implement any arbitrary 3-input function

5. Background: K-Input PLB

6. Motivation The cost of implementing a circuit in an FPGA is directly proportional to the number of PLBs required to implement the functionality of the circuit. The cost of implementing a circuit in an FPGA is directly proportional to the number of PLBs required to implement the functionality of the circuit. Decreasing the number of PLBs may allow a circuit to be realized in a smaller FPGA. Decreasing the number of PLBs may allow a circuit to be realized in a smaller FPGA. The PLB architecture has a significant impact on the number of PLBs required to realize a particular circuit. The PLB architecture has a significant impact on the number of PLBs required to realize a particular circuit.

7. PLB Evaluation in terms of Area Clever PLB designs are necessary to capture the majority of the functions encountered in typical circuits. Clever PLB designs are necessary to capture the majority of the functions encountered in typical circuits. Extract set of k-Input functions from a large set of circuits. Extract set of k-Input functions from a large set of circuits. Examine the percentage of functions that map into the PLB structure. Examine the percentage of functions that map into the PLB structure.

8. Function Mapping Problem x1x2x3x1x2x3x1x2x3x1x2x3f0000 0010 0101 0110 1001 1011 1101 1111 QSAT ?

9.  Defined over a set of variables, V Background: The Propositional Satisfiability (SAT) problem Given a formula, f : C1C1 C2C2 C3C3 a=b=c=1 (a,b,c) (C 1,C 2,C 3 )  Comprised of a conjunction of clauses  Each clause is a disjunction of literals of the variables V Example : SAT: Seek an assignment of to the variables, V, which sets the Boolean formula to ‘1’.

10.  Defined over a set of variables, V Background: The Quantified Satisfiability (QSAT) problem Given a formula, f : C1C1 C2C2 C3C3 b=c=1 a = {0,1} (a,b,c) (C 1,C 2,C 3 )  Comprised of a conjunction of clauses  Each clause is a disjunction of literals of the variables V Example : QSAT: Seek an assignment of to the variables, V, which sets the quantified Boolean formula (QBF) to ‘1’. Quantifiers exist on variables V  Quantifiers exist on variables V AE

11. Function Mapping Problem x1x2x3x1x2x3x1x2x3x1x2x3f0000 0010 0101 0110 1001 1011 1101 1111 QSAT ?

12. Construction of CNF T. Larrabee, “Test pattern generation using Boolean satisfiability," TCAD, 1992 (Plaisted's and Greenbaum's encoding which is based on Tseitin's work) Creates a Characteristic Function for circuits x1x2x1x2x1x2x1x2gf0001 0101 1001 1100 0010 0110 1010 1111 f=(x 2 +¬g) (x 1 +¬g) (¬x 2 +¬x 1 +g)

13. Construction of CNF (cont’d) f AND = (x 2 +¬z 1 ) (x 1 +¬z 1 ) (¬x 2 +¬x 1 + z 1 ) f OR = (¬x 3 +g) (¬z 1 +g) (x 3 +z 1 + ¬g) f OR f total = f AND f OR (¬x 3 +g) (¬z 1 +g) (x 3 +z 1 + ¬g) = (x 2 +¬z 1 ) (x 1 +¬z 1 ) (¬x 2 +¬x 1 + z 1 ) (¬x 3 +g) (¬z 1 +g) (x 3 +z 1 + ¬g)

14. Function Mapping Problem x1x2x3x1x2x3x1x2x3x1x2x3f0000 0010 0101 0110 1001 1011 1101 1111 QSAT ?

15. Formulating Function Mapping Problem Can function f be implemented in circuit g ? Can function f be implemented in circuit g ? Does there exist a configuration to g such that for all inputs to g, f is equivalent to g Does there exist a configuration to g such that for all inputs to g, f is equivalent to g x1x2x3x1x2x3x1x2x3x1x2x3f 0000 0010 0101 0110 1001 1011 1101 1111 ?

16. Formulating Function Mapping Problem Derive characteristic function H for circuit g Derive characteristic function H for circuit g Replace all instances of g in H with f Replace all instances of g in H with f –H[g/f] (g ≡ f ) –f is equivalent to g x1x2x3x1x2x3x1x2x3x1x2x3f 0000 0010 0101 0110 1001 1011 1101 1111 ?

17. Formulating Function Mapping Problem Does there exist a configuration to g such that for all inputs to g, f is equivalent to g ? Does there exist a configuration to g such that for all inputs to g, f is equivalent to g ? (g ≡ f ) (g ≡ f ) x1x2x3x1x2x3x1x2x3x1x2x3f 0000 0010 0101 0110 1001 1011 1101 1111 ?

18. Formulating Function Mapping Problem Does there exist a configuration to g such that for all inputs to g, f is equivalent to g ? Does there exist a configuration to g such that for all inputs to g, f is equivalent to g ? l 1 …l m x 1 …x n (g ≡ f ) AE x1x2x3x1x2x3x1x2x3x1x2x3f 0000 0010 0101 0110 1001 1011 1101 1111 ?

19. Formulating Function Mapping Problem Express as a QBF with inputs ( x 1 …x n ) and configuration bits ( l 1 …l m ) Express as a QBF with inputs ( x 1 …x n ) and configuration bits ( l 1 …l m ) l 1 …l m x 1 …x n (g ≡ f ) l 1 …l m x 1 …x n (g ≡ f ) AE x1x2x3x1x2x3x1x2x3x1x2x3f 0000 0010 0101 0110 1001 1011 1101 1111 QSAT

20. Results: Evaluation of PLBs Given a circuit, extract 1000 k-input functions Given a circuit, extract 1000 k-input functions k == number of inputs to PLB k == number of inputs to PLB Determine number of functions that map into PLB using QSAT Determine number of functions that map into PLB using QSAT Find a fit percentage Find a fit percentage

21. Results: Evaluation of PLBs

22. Conclusions Novell function mapping technique based on QSAT. Novell function mapping technique based on QSAT. We can use this technique to evaluate PLB architectures based on area. We can use this technique to evaluate PLB architectures based on area.

23. Future Work Speed up QSAT, use ALL-solution SAT solvers or better QBF solvers Speed up QSAT, use ALL-solution SAT solvers or better QBF solvers Cannot evaluate area efficiency without looking at routing architecture Cannot evaluate area efficiency without looking at routing architecture Use “Don’t Cares” when mapping functions Use “Don’t Cares” when mapping functions Use genetic algorithms to create candidate PLBs, then pipe architectures to our PLB evaluator tool Use genetic algorithms to create candidate PLBs, then pipe architectures to our PLB evaluator tool

24. Questions?