3/10/2006EECS150 Lab Lecture #81 Chipcon Transceiver EECS150 Spring 2006 Lab Lecture #8 David Lin

3/10/2006EECS150 Lab Lecture #82 Project Overview N64 Controller User input to your game. Video Game output to the user. Chipcon Transceiver: the “FUN” Two-Week One! =) Bidirectional communication between games. Game Engine Drives game play. “Glue logic.” Handles communication handshaking.

3/10/2006EECS150 Lab Lecture #83 Transceiver Overview (1) 3 rd party chip mounted on expansion board. Uses a PCB antenna. Take a look! IEEE standard support. Zigbee ready. Transmits on unlicensed 2.4 GHz spectrum. 16 communication channels. Overlaps with Wi-Fi. 250 kbps maximum data rate. We will only be using a very small percentage of this. Configure, send, receive, and issue commands to chip over SPI to CC2420 registers.

3/10/2006EECS150 Lab Lecture #84 Transceiver Overview (2) 33 configuration registers. We change 3 of them. 15 command strobe registers. We issue 6 of them. These change the state of the CC2420 internal FSM. 128-byte RX FIFO & 128-byte TX FIFO Accessed via 2 additional registers. Also accessible as RAM (i.e. by addressing). Only for debugging! Probably not necessary.

3/10/2006EECS150 Lab Lecture #85 CC2420 Inputs & Outputs FPGA VREG_EN RF_RESET_ Single bit status signals. High level transceiver operation information. Initialization signals. Drive signals once and forget about it. SPI interface. Interface to rest of chip via CC2420 registers. Send, receive, configuration, detailed status.

3/10/2006EECS150 Lab Lecture #86 Single Bit Status Indicators FIFO – Goes high when there’s received data in RX FIFO. FIFOP – Goes high when # bytes received exceeds set threshold. CCA – Indicates that the transmission medium (air) is clear. Only valid after 8 symbol periods in RX mode. SFD – Goes high after SFD is transmitted & low after packet completely sent.

3/10/2006EECS150 Lab Lecture #87 SPI Interface Serial interface with 4 wires: SClk – Clock signal you generate. CS_ – Active-low chip select. SI – Output to the CC2420. SO – Input from the CC2420. Described earlier in class lecture. Interface to the chip! Initialization, configuration, TX, RX, detailed status. Luckily for you, it’s provided as a black box.

3/10/2006EECS150 Lab Lecture #88 CC2420-specific SPI (1): First Byte First byte always has above format. Bit 7 – Set to 0 for register access. Bit 6 – Read/write control. Bits 5:0 – Address of register. P. 60 of datasheet. Followed by data specific to register being accessed. Sent First  Bit Position  Sent Later 765:0 1 = RAM access (not used) 0 = register access 1 = read 0 = write Address of register. Refer to p. 60 of the datasheet.

3/10/2006EECS150 Lab Lecture #89 CC2420-specific SPI (2): Writing to Configuration Reg. First byte followed by 2 bytes of configuration data. Data on SO invalid here. Transceiver replies when first byte is sent out with status byte. True for all SPI accesses. Not necessary to inspect, but can be helpful for debugging! Sent First  Byte Number  Sent Later Sent on SI address byte, described above16 bits of data to be written to register Received on SO status byte16’bX

3/10/2006EECS150 Lab Lecture #810 CC2420-specific SPI (3): Issuing Command Strobes One byte only. Nothing follows. Address sent indicates the command strobe being issued. Note that 0x00 is NO OP. This is useful for explicitly retrieving status byte. Byte Number 1 Sent on SI address byte, described above Received on SO status byte

3/10/2006EECS150 Lab Lecture #811 CC2420-specific SPI (4): Saving to TX FIFO After first byte, send n bytes of data to transmit over wireless. SPI session only ends when CS_ is pulled high. CC2420 replies with a new status byte with each byte that’s saved to FIFO. Sent First  Byte Number  Sent Later 12 to n Sent on SI address byte, described abovedata bytes to be transmitted Received on SO status byte

3/10/2006EECS150 Lab Lecture #812 CC2420-specific SPI (5): Receive from RX FIFO After first byte, send a n bytes of “don’t care” in order to receive data. During first byte, CC2420 replies with status. Subsequent bytes are data saved in FIFO. Must be careful not to request data from empty FIFO! SPI session only ends when CS_ is pulled high. Reading from a configuration register is the same. Received First  Byte Number  Received Later 12 to n Sent on SI address byte, described above8’bX Received on SO status bytedata from the RX FIFO

3/10/2006EECS150 Lab Lecture #813 Configuration Registers RegisterAddressBit(s) of Interest Purpose MDMCTRL00x1111Turn off automatic address recognition. You must set bit 11 to 1’b0. FSCTRL0x189:0Channel changing. IOCFG00x1C6:0Changes the threshold of number of bytes in RX FIFO before FIFOP goes high. Defaults to 64. You may want to change this value.

3/10/2006EECS150 Lab Lecture #814 Command Strobe Registers RegisterAddressPurpose SNOP0x00No operation. SXOSCON0x01Turns on the crystal oscillator and will be used as part of the initialization process. SRXON0x03Moves the CC2420 into the receive state and will be used as part of the initialization and channel changing process. STXON0x04Instructs the CC2420 to transmit the data contained in the TX FIFO. SRFOFF0x06Turns off RX/TX and frequency synthesizer and will be used as part of channel changing. SFLUSHRX0x08Flushes the RX FIFO. This command will be used a lot!

3/10/2006EECS150 Lab Lecture #815 TX/RX FIFO Registers RegisterAddressPurpose TXFIFO0x3EFor saving bytes to transmit into the TX FIFO. You must not write data to the FIFO while a transmission is in progress. RXFIFO0x3FFor retrieving bytes from the RX FIFO.

3/10/2006EECS150 Lab Lecture #816 Initialization

3/10/2006EECS150 Lab Lecture #817 Transmit

3/10/2006EECS150 Lab Lecture #818 Receive (1)

3/10/2006EECS150 Lab Lecture #819 Receive (2) Packets are only received after CC2420 has spent 12 symbol periods in receive mode. There must be wait time between transmissions. Allows the transceiver to look for and receive data.

3/10/2006EECS150 Lab Lecture #820 Announcements Next week’s lab lecture is Thursday 8- 9P. Come with questions! Groups have been assigned channels and addresses. Check online grade book.

3/10/2006EECS150 Lab Lecture #821 Design Structure (1)

3/10/2006EECS150 Lab Lecture #822 Design Structure (2) Transceiver – Highest level block. 32-bit input/output, channel changing, addressing. SPI Abstraction – Takes care of details of CC2420 SPI interface. Arbitrates between TX/RX. SPI (provided) – Handles details of interface timing. SPIFifo (provided) – Storage place for filtered, received data.

3/10/2006EECS150 Lab Lecture #823 Packet Format MPDU PreambleSFDLengthSourceDest.PayloadFrame Check Sequence (CRC) 4 bytes1 byte 4 bytes2 bytes 0x000x7A0x08 sender’s addr. recipient’s addr. or 0xFF for broadc ast data  On transmit, 0x00.  On receive, bit 7 of the 2 nd byte is 1 when CRC ok, 0 otherwise. On transmit, only fill TX FIFO starting with length byte. Preamble & SFD automatically appended. Transmit all zeros for CRC. CC2420 will replace.

3/10/2006EECS150 Lab Lecture #824 Channel & Addresses There are 16 channels. Your group has been assigned a channel. You must be able to change channels without reset! Address are 8-bits wide  256 addresses. Zero is unused. 0xFF is reserved for broadcast. Your group has been assigned 2 addresses.

3/10/2006EECS150 Lab Lecture #825 Interference & Debugging Roughly 2-3 groups per channel. Each group in a particular lab has distinct channel. Can also pick up data on neighboring channel. Very first goal is robust channel changing during initialization. Can pick up packets sometimes. Your module must recover gracefully. Your project interferes with Wi-Fi & vice versa.

3/10/2006EECS150 Lab Lecture #826 Handshaking: InRequest/Invalid SPI uses a variation of this. You may want to use this internally.

3/10/2006EECS150 Lab Lecture #827 Handshaking: Ready/Start Transceiver uses this interface for input & output.

3/10/2006EECS150 Lab Lecture #828 Debugging Tools Chipscope! We will be releasing some debugging utilities. Packet sniffer. Packet counter.

3/10/2006EECS150 Lab Lecture #829 Get Started! Don’t count on spring break. This is meant to replace a ~50 hour (avg.) SDRAM checkpoint. There are many subtleties that you must address (e.g. when are RX flushes used?). I will monitor newsgroup over spring break, but less frequently. Next week’s lab lecture is CP3 Q&A. Come with questions. Read the datasheet!