1. (Adapted From Slides by Greg Gibeling)
EECS 150 Spring 2008
Checkpoint 1 - SDRAM
2/29/2008
Chen Sun
(Adapted From Slides by Greg Gibeling)

2. Welcome to Checkpoint 1 Agenda Why Checkpoint 1 is Important
Checkpoint 1 Specs
Theory of SDRAM
SDRAM Init, Read, Write (timing diagrams)
Designing the SDRAM controller

3. Motivation Learn to configure external SDRAM
(Checkpoint #1)
Multiport
Arbitration
Learn to configure external SDRAM
Write and read from external SDRAM
To use FIFOs as buffers
Design a memory controller
You will need this for the project

4. What is Checkpoint 1? (1) Initialize and configure SDRAM
We provide 32-bit data generator
checkpoint0bb
The black box we provide will handle all read and write requests
We will provide addressing scheme

5. What is Checkpoint 1 (2)
We provide data checker to compare what is read from SDRAM from what should have been written
Count the errors and display on LEDs

6. What is Checkpoint 1? (3)

7. Theory of SDRAM (1) SDRAM: Synchronous Dynamic RAM Upside Down side
Huge amounts of storage
Down side
Slow
May need refreshing every once in a while

8. Theory of SDRAM (2) So to speed things up…
SDRAM handles bursts to read data as a group
Control requires precise timing
Issue sequences of commands
Timing must be matched with Data Sheet (more on this later)

9. Theory of SDRAM (3) DRAM is BIG so we time mux address
Row Address
Column Address
Steps to Read/Write
Send Row Address
Send Column Address
Send/Get Data
Read the Data sheet for details

10. Theory of SDRAM (4) SDRAM is a large FSM SDRAM Controller’s Job:
Send it a command
Get a response
SDRAM Controller’s Job:
Send the right command signals
Ensure command sequences are timed correctly

11. SDRAM Specifications See Spec at
Read the MT48LC16M16 Datasheet
Provides overview of commands and timing
You will need to become very familiar with initialization, reads, and writes

12. SDRAM Initialization (p 40)

13. Read Operation (p 46)

14. Write Operation (p 53)

15. Write Timing
Memory chips are the -7E Models, and the clock is running at 27MHz

16. SDRAM Controller (1) One Time Repeating Initialization
Read with auto-precharge
Write with auto-precharge
Auto-Refresh (only if idle for a long time)
Refreshes should not be necessary for this project

17. SDRAM Controller (2) Goal Design Options
Abstracts away the details of SDRAM
Accepts commands, produces responses
Deals with sending address in parts (row and then column)
Design Options
Completely up to you!

18. SDRAM Controller (3)
Design for the future! You will need it for your project
Tristate data line when reading!
SDRAM accepts input and puts outputs on the same bus

19. FIFOs Buffer to match two data rates
Great for data path clock domain crossings (we’ll talk about it later this semester)

20. The Checkpoint (1) You have one week to complete this CP
Design Reviews next week at the beginning of your lab section
Bubble-and-arc diagram(s) required
Block Diagram highly recommended
Timing diagram required
Example: read and write
DO NOT COPY the one on the spec sheet

21. The Checkpoint (2) Construction Groups of two – your lab #4/#5 partner
Demo circuit on board for check-off
Remember you will be designing for CP1 concurrently
Groups of two – your lab #4/#5 partner
You must get checked off in the same lab section for the rest of the semester
Start designing today!

22. Any Questions? Your friendly neighborhood lab TA is here
We want high completion for CP1, get help if you need it!
Sign-up sheet for partner/grading