Lecture #26 Gate delays, MOS logic Today: Gate delays Another look at CMOS logic transistors 11/1/2004 EE 42 fall 2004 lecture 26

Controlled Switch Model of Inverter RN + - VDD = 3V VSS = 0V VIN =3V VOUT VIN =0V RP VIN jumps from 0V to 3V VIN jumps from 3V to 0V VOUT t 3 Output when: tD What is the gate delay tD for this simple inverter? If we define tD as the time to go halfway to the asymtotic limit, tD = 0.69RC . To get equal delays we will need to set RP = RN. 11/1/2004 EE 42 fall 2004 lecture 26

Simple model for logic delays (slide 2 again) We model actual logic gate as an ideal logic gate fed by an RC network which represents the dominant R and C in the gate. R C Ideal Logic gate Model of Actual Logic Gate VX ) t ( v OUT etc. t vIN VX tD = 0. 69 RC vOUT This model is very close to real physics: the transistors are inherently extremely fast, but are slowed by the need to charge up (or discharge) the capacitance at the various nodes. 11/1/2004 EE 42 fall 2004 lecture 26

CMOS Logic Gate NMOS and PMOS use the same set of input signals VDD B C VDD VOUT PMOS only in pull-up PMOS conduct when input is low PMOS do not conduct when A +(BC) NMOS only in pull-down NMOS conduct when input is high. NMOS conduct for A + (BC) Logic is Complementary and produces F = A + (BC) 11/1/2004 EE 42 fall 2004 lecture 26

CMOS Logic Gate: Example Inputs B C VDD VOUT A = 0 B = 0 C = 0 PMOS all conduct Output is High = VDD NMOS do not conduct Logic is Complementary and produces F = 1 11/1/2004 EE 42 fall 2004 lecture 26

CMOS Logic Gate: Example Inputs B C VDD VOUT A = 0 B = 1 C = 1 PMOS A conducts; B and C Open Output is High = 0 NMOS B and C conduct; A open Logic is Complementary and produces F = 0 11/1/2004 EE 42 fall 2004 lecture 26

Switched Equivalent Resistance Network B C VDD VOUT RU RD A B C VDD VOUT Switches close when input is low. Switches close when input is high. 11/1/2004 EE 42 fall 2004 lecture 26

Logic Gate Propagation Delay: Initial State B C VDD VOUT RU RD COUT = 50 fF The initial state depends on the old (previous) inputs. The equivalent resistance of the pull-down or pull-up network for the transient phase depends on the new (present) input state. Example: A=0, B=0, C=0 for a long time. These inputs provided a path to VDD for a long time and the capacitor has charged up to VDD = 5V. 11/1/2004 EE 42 fall 2004 lecture 26

Logic Gate Propagation Delay: Transient B C VDD VOUT RU RD COUT = 50 fF At t=0, B and C switch from low to high (VDD) and A remains low. This breaks the path from VOUT to VDD And opens a path from VOUT to GND COUT discharges through the pull-down resistance of gates B and C in series. Dt = 0.69(RDB+RDC)COUT = 0.69(20kW)(50fF) = 690 ps The propagation delay is two times longer than that for the inverter! 11/1/2004 EE 42 fall 2004 lecture 26

Logic Gate: Worst Case Scenarios B C VDD VOUT RU RD COUT = 50 fF What combination of previous and present logic inputs will make the Pull-Up the fastest? Fastest overall? What combination of previous and present logic inputs will make the Pull-Up the slowest? Slowest overall? What combination of previous and present logic inputs will make the Pull-Down the fastest? What combination of previous and present logic inputs will make the Pull-Down the slowest? 11/1/2004 EE 42 fall 2004 lecture 26

MOS transistors The heart of digital logic is the MOS transistor, both NMOS and PMOS In the next couple of lectures, we will learn more about how CMOS logic works at the circuit level, starting with a review of the NMOS transistor 11/1/2004 EE 42 fall 2004 lecture 26

NMOS TRANSISTOR STRUCTURE P-type Silicon oxide insulator gate “Metal” gate (Al or Si) NMOS = N-channel Metal Oxide Silicon Transistor An insulated gate is placed above the silicon Its purpose is to control the current between n-type regions (by inducing a “channel” of electrons when a positive V is applied). 11/1/2004 EE 42 fall 2004 lecture 26

MOS TRANSISTOR STRUCTURE “Metal” “Semiconductor” “Oxide” DEVICE IN CROSS-SECTION n P oxide insulator gate “Metal” gate (Al or Si) D S G The “gate” electrode is just a conductor to act as the capacitor top plate The lower “body” electrode is silicon with almost no electrons present (essentially an insulator) Thus no current can flow between the D and S electrodes which contact the silicon 11/1/2004 EE 42 fall 2004 lecture 26

MOS TRANSISTOR STRUCTURE DEVICE with + Gate Voltage n P oxide insulator “Metal” gate (Al or Si) D S G + - 5V + + + + + + + + + + + + _ _ _ _ _ _ _ _ _ _ _ _ Here the 5V across the capacitor induces + charge on the gate and – charge on the surface of the semiconductor, according to Q=CV. The charge in the semiconductor is really just free electrons which can carry current (just like the electrons in a metal can carry current). Thus by applying a voltage to the gate we have provided a conduction path for current if a voltage is applied from D to S. 11/1/2004 EE 42 fall 2004 lecture 26

MOS Transistor as a controlled switch VGS S Si oxide +  G VDS D i tox VGS >> VT iD VDS VGS > VT iD Zero if VGS is small But the device is not fundamentally ON/OFF. As VGS increases, the switch resistance decreases (slope becomes steeper). Thus we have a “family of I-V curves” which describe the current into D as a function of both VDS and VGS 11/1/2004 EE 42 fall 2004 lecture 26

Three-Terminal Device Graphs VDS ID (mA) 10 (V) 1 2 3-Terminal Device ID D G S VGS +- ID versus VDS for VGS = 2V. Concept of 3-Terminal Device Graphs: We set a voltage (or current) at one set of terminals (here we will apply a fixed VGS of 2V) and conceptually draw a box around the device with only two terminals emerging So we can now plot the two-terminal characteristic (here ID versus VDS). 11/1/2004 EE 42 fall 2004 lecture 26

Three-Terminal Parametric Graphs 3-Terminal Device ID D G S VDS ID (mA) 10 (V) 1 2 VGS + - VGS = 3 VGS = 2 VGS = 1 Concept of 3-Terminal Parametric Graphs: We set a voltage (or current) at one set of terminals (here we will apply a fixed VGS) and conceptually draw a box around the device with only two terminals emerging so we can again plot the two-terminal characteristic (here ID versus VDS). But we can do this for a variety of values of VGS with the result that we get a family of curves. 11/1/2004 EE 42 fall 2004 lecture 26

NMOS I vs V Characteristics Example of experimental I-V characteristics. (You can do in the 43 Lab) ID VDS VGS VGS = 0 VGS = 1 VGS = 1.5 VGS = 2 VGS S G VDS iD +  D For low gate voltages, no drain current flows. As VGS is increased above threshold, e.g. 1V, the nonlinear “saturating” I-V curve is obtained. Increasing VGS causes ID to increase, as the family of curves indicates. 11/1/2004 EE 42 fall 2004 lecture 26

The Family of ID vs VGS Curves For short-channel devices used in digital logic, the ID vs VDS curves are decidedly nonlinear! Curves which start out as simple linear resistors saturate as shown on this and the previous slide. We can approximate the I-V characteristics as two straight lines. 0.5 VDS ID(mA) 4 3 2 1 0.75 1.25 a) the linear “resistance” region at low VDS and b) the saturation region (almost horizontal) at larger VDS. 11/1/2004 EE 42 fall 2004 lecture 26

NMOS Summary IDS ID VDS VDD G S D ID ID for VGS = maximum (VDD) If VGS = 0. N Ch The circuit symbol Electrical Model D S G RDN A value for RDN is chosen to give the correct timing delay. 11/1/2004 EE 42 fall 2004 lecture 26

Remember the Role of the Switch The NMOS transistor conducts the charge out of the capacitor to ground when its input (VGS) is high (VDD). RN + - VDD = 3V VSS = 0V VIN =3V VOUT We cover up the non-useful parts of the circuit for simplicity. G D The capacitor was initially at 3V (VDD), and goes toward zero. We define one stage delay by the time for VOUT = VDS to reach 1.5V (VDD /2). S VGS = VDD IDS ID VDS VGS = 0 VDD VDD/2 Now lets draw the I-V characteristics of the NMOS When VGS jumps to VDD, the current jumps from zero to this value. As the capacitor discharges, V decreases and the current follows the IDS vs VDS curve. As a first approximation we will assume that l=0 11/1/2004 EE 42 fall 2004 lecture 26

Computing the stage delay The stage delay is the time for VOUT to decrease from VDD to VDD /2. The capacitor is initially charged to 3V, and we want to see how long it takes to reach 1.5V. That is the delay. VOUT RN + - VIN =3V D G S C + - As V goes from VDD to VDD /2, the average current IAV  IDS( 1+lX(3/4)VDD) ( IDS if l is close to zero; consider this case first). We integrate the capacitor equation to find the time: IDS ID VDS VGS = VDD VGS = 0 As the capacitor discharges, V decreases and the current follows the IDS vs VDS curve. VDD VDD/2 =CVDD/2IDS for l = 0 11/1/2004 EE 42 fall 2004 lecture 26

Computing the stage delay (for l 0) The stage delay t is the time for VOUT to decrease from VDD to VDD /2. Thus t = CVDD/2IDS for l = 0 VOUT RN + - VIN =3V D G S C + - Now suppose we had instead assumed a resistance which averaged VDD/IDS and VDD/2IDS ,that is 3VDD/4IDS , shown as the blue line in the figure below. We would compute t = 0.69RC = 0.69 (3VDD/4IDS )C That is t = 0.52 CVDD/IDS which is only 4% larger than the value we found by doing the actual integration. IDS ID VDS VGS = VDD VGS = 0 Here we approximate l = 0 so the slope is zero VDD VDD/2 11/1/2004 EE 42 fall 2004 lecture 26

Computing the stage delay (for l >0) We found by integration that Since IAV  IDS( 1+lX(3/4)VDD) we have t =0.5C VDD / IDS( 1+lX(3/4)VDD). Now lets compare with the value we would get using an averaged-value resistor (blue line below) VOUT RN + - VIN =3V D G S C + - As VOUT goes from VDD to VDD /2, the average resistance is (3/4) VDD / IDS( 1+lX(3/4)VDD) thus our time constant (0.69RC) equals As the capacitor discharges, VOUT decreases and the current follows the IDS vs VDS curve. IDS ID VDS VGS = VDD VGS = 0 VDD VDD/2 =0.69 C (3/4) VDD / IDS( 1+lX(3/4)VDD) = 0.52 C VDD / IDS ( 1+lX(3/4)VDD) Again, this is only 4% different from the answer obtained by direct integration 11/1/2004 EE 42 fall 2004 lecture 26

Computing the stage delay - Summary During the discharge of C through the NMOS transistor, we have shown that we can compute the stage delay t by using the switch model with an effective resistance RDN = (3/4) VDD / IDS( 1+lX(3/4)VDD) VOUT RN + - VIN =3V D G S C + - Thus we can compute the stage delay, 0.69RDNC, IDS ( 1+lVDD) IDS ID VDS VGS = VDD VGS = 0 VDD VDD/2 Electrical Model D S G RDN 11/1/2004 EE 42 fall 2004 lecture 26