Ben Kilminster 11 Feb 2005; p.1 Cornell JC : CDF XFT Upgrade 3-D Upgrading the CDF Track Trigger to 3-D for High Instantaneous Luminosity Ben Kilminster Ohio State University CDF Collaboration L = 1x10 32 cm -2 s -1 Last week ! Project includes physicists and engineers from: Ohio State, Baylor, Fermilab, Illinois, Purdue, UC Davis

Ben Kilminster 11 Feb 2005; p.2 Cornell JC : CDF XFT Upgrade CDF Central Outer Tracker (COT)  8 “ superlayers ” of cells  4 with axial wires: r -  measurement  4 with stereo wires: z measurement  Each cell  0.88 cm drift (avg.)  Max drift time ~220 ns  12 sense wires/cell: 96 measurements  2540 cells, channels

Ben Kilminster 11 Feb 2005; p.3 Cornell JC : CDF XFT Upgrade eXtremely Fast Tracker = Level 1 Track Trigger  Role of tracking  Top, W/Z, Exotic Physics triggers require High momentum electron and muon Level 1 trigger candidates  Bottom Physics require low momentum tracking at the Level 1 trigger  electrons  muons  hadronic tracks  L1 Trigger Primitives  Electrons: XFT track + EM cluster  Muons: XFT track + muon stub  L2 Trigger Tracks  XFT Track + Silicon Hits CDF Trigger System

Ben Kilminster 11 Feb 2005; p.4 Cornell JC : CDF XFT Upgrade Overview of Existing XFT  Hit Finding: Mezzanine Card  Hits are classified as prompt or delayed (i.e. “2-bin”)  Segment Finding  In the axial layers  patterns of wires within one superlayer  Track Finding  Looking across 3 or 4 axial layers, search for patterns of segments consistent with Pt>1.5 GeV/c Good hit patterns are identified as segment, then segments are linked as tracks Tracks only found in 2-Dimensions (r,  )

Ben Kilminster 11 Feb 2005; p.5 Cornell JC : CDF XFT Upgrade The Hit and Segment Finders Hits : 2 bins - Prompt or delayed Mask : A specific pattern of prompt and delayed hits on the 12 wires of an axial COT layer generated by simulating tracks Pixel: represents the phi position of the track at the midpoint of the cell. Track segments are found by comparing hit patterns in a given layer to a list of valid patterns or “masks”. “Delayed” hit “Prompt” hit LayerCellsMasksPixels

Ben Kilminster 11 Feb 2005; p.6 Cornell JC : CDF XFT Upgrade Segment Finder Output  In the inner two layers, each mask corresponds to 1 of 12 pixel positions in the middle of the layer.  The pixel represents the phi position of the track.  In the outer 2 layers, each mask corresponds to 1 of 6 pixel positions and 1 of 3 slopes: (low pt +, low pt -, high pt).  When a mask is located, the corresponding pixel is turned on.

Ben Kilminster 11 Feb 2005; p.7 Cornell JC : CDF XFT Upgrade The Segment Linker Slopes must match Pixels must match Tracks are found by comparing fired pixels in all 4 layers to a list of valid pixel patterns or “roads”. Chamber is divided into –degree “identical” Linkers Highest track reported for each linker -> Max of 288 tracks per event Each linker uses a look-up table of ~1200 roads

Ben Kilminster 11 Feb 2005; p.8 Cornell JC : CDF XFT Upgrade XFT System Electronics  Mezzanine Cards  168 cards  Classifies hits as prompt/delayed  Final Finder system  24 SL1-3 boards  24 SL2-4 boards  Heavy reliance on PLDs  Allows for some redesign: new patterns for number of misses, wire sag, faster gas, etc  Final Linker System  24 Linker boards  Heavy reliance on PLDs  Allows for new road set based on new beam positions  Have already developed 2 new roads sets due to accelerator changes.

Ben Kilminster 11 Feb 2005; p.9 Cornell JC : CDF XFT Upgrade XFT Performance in CDF RunII Performance of the XFT in CDF’s RunII has been excellent 1.Momentum resolution 1.74%/GeV/c 2.Phi Resolution < 6mRad 3.Efficiency ~ 95% (almost 100% for high Pt tracks)

Ben Kilminster 11 Feb 2005; p.10 Cornell JC : CDF XFT Upgrade Why an Upgrade?  The XFT was designed for a luminosity of:  L=1x10 32 cm -2 s -1 with 396 nsec bunch crossings  ~ 3  Then it was supposed to switch to :  L=2x10 32 cm -2 s nsec bunch  ~ 2  But 132ns was not feasible  Accelerator Performance  Max luminosity attained: 1x10 32 cm -2 s -1  Expect to reach L=3x10 32 cm -2 s -1 at 396nsec bunch crossing  ~ 9  Factor of 3-4 above design 132 ns 396 ns

Ben Kilminster 11 Feb 2005; p.11 Cornell JC : CDF XFT Upgrade Z  ee at low lum. 0 add. Int./crossing

Ben Kilminster 11 Feb 2005; p.12 Cornell JC : CDF XFT Upgrade Z  ee at low lum. 2 add. Int./crossing

Ben Kilminster 11 Feb 2005; p.13 Cornell JC : CDF XFT Upgrade Z  ee at low lum. 5 add. Int./crossing

Ben Kilminster 11 Feb 2005; p.14 Cornell JC : CDF XFT Upgrade Z  ee at low lum. 10 add. Int./crossing

Ben Kilminster 11 Feb 2005; p.15 Cornell JC : CDF XFT Upgrade Z  ee at low lum. 10 add. Int./crossing

Ben Kilminster 11 Feb 2005; p.16 Cornell JC : CDF XFT Upgrade Two-Track Triggers  Two Track Trigger for B Physics  2 tracks p T >2.5 GeV  Opposite charge  p T (1)+ p T (2)>6.5 GeV   < 135  Quadratic growth (overlaps + fakes)   ( L =5E31)/  ( L =0)=1.5  Extrapolate:  linear  ( L =1.5E32) = 225  b  34kHz  Real (from overlapped MB)  ( L =1.5E32) = 500  b  75kHz 100  b 160  b We are stuck with FIXED Bandwidth (Accept Rate): L1: 30 kHz L2: 1 kHz L3: 100 Hz Run II Data

Ben Kilminster 11 Feb 2005; p.17 Cornell JC : CDF XFT Upgrade What’s needed:  Primary problem is the growth of fake tracks due to pattern recognition problems:  Need a way to model the highest luminosity running  Simulations of the XFT System  Study the effect of high luminosity running on a variety of triggers  Two-Track Trigger (low P T )  Single Track Trigger (high P T : Track Only)  Electron Trigger (Track + Other object)  Consider modifications/additions to the current system  Reduce fake rate  Maintain resolution fake Fake tracks can be made from pieces of different real physical tracks. Trigger Rate is the “Figure of Merit”

Ben Kilminster 11 Feb 2005; p.18 Cornell JC : CDF XFT Upgrade XFT Simulation of High Lum.  All events are passed through a hit-level simulation  Start with COT hits  Gives exactly the same answer as hardware when run with same masks, roads and XFT hits  Outputs XFT hits, pixels, and tracks for axial and XFT pixels for stereo  Simulate High luminosity by Merging events “main” event with zero bias  Merge COT hits (combine overlapping hits)  simulate XFT with various options  Add tracks from individual events together  Offline tracks serve as “truth” for the event  This method allows us to probe up to 4E32

Ben Kilminster 11 Feb 2005; p.19 Cornell JC : CDF XFT Upgrade Upgrade Strategy Current XFT uses 4 axial layers only Upgrade adds 3 stereo layers. Use full 396ns between crossings to send more precise hit information.  Studied various upgrade paths  Replacing Axial System (Use additional 264ns between crossings)  Add information from Stereo Layers of COT  Replace linker with finer segment linking  Doing some of the above  Advantages of Stereo Upgrade  Gives us the fake track rejection we need.  Allows for more additional handles in trigger  Track pointing to muon stubs & calor (L2)  Possibility of Two-Track Invariant Mass Cuts (Understudy)  Parallel Path to Axial System  Commission parasitically.  Only Minor changes to Axial System  Slight Changes to existing firmware.  KEEP A WORKING SYSTEM  No extended downtime We picked this. Stereo layers

Ben Kilminster 11 Feb 2005; p.20 Cornell JC : CDF XFT Upgrade Impact of Stereo  The stereo can have an impact in two ways:  Confirmation Segment: Since often fake XFT tracks are the result of linking two unrelated low Pt segments, requiring another high Pt stereo segment in the allowed window around an axial track can be very powerful.  We will use this at Level 1  Provide Z-pointing to tracks: Since EM and muon calorimeters are segmented in Z, coarse pointing can be very helpful in eliminating fakes  We can use this effectively at Level 2 one stereo layer rejection

Ben Kilminster 11 Feb 2005; p.21 Cornell JC : CDF XFT Upgrade Stereo association studies Reals Fakes SL5 SL6 SL7 Expected pixel position (z = 0)  pixel (SL7) Displacement from stereo angle Measured pixel position (z  0) SL5 has opposite displacement from SL7  pixel (SL5) SL3 SL4  pixel (SL3) Displacement from stereo angle Measured pixel position (z  0) Pixel displacement is a measure of eta of track

Ben Kilminster 11 Feb 2005; p.22 Cornell JC : CDF XFT Upgrade Overview of Upgrade  Hit Stage  Provide 6 times bins per wire per bunch crossing instead of the present 2 for stereo layers  maintain existing 2-bin system for axial layers  Pass stereo hit information to Finders via optical cable  maintain existing Ansley cables for axial layers  Segment Finding Stage  Using 6 times bins, measure phi (pixel) position and slope of segments in 3 outer stereo layers  maintain existing axial segment finding system  Axial Segment Linking stage  maintain existing axial track finding system  Add new Stereo Linker Association Stage  Associate existing axial tracks from the axial system with stereo segments to reduce number of fake track

Ben Kilminster 11 Feb 2005; p.23 Cornell JC : CDF XFT Upgrade Current XFT Configuration Ansley trigger cable (220 ft) LVDS 168 TDC from COT axial layers 24 crates Axial Finders 3 crates XTC ~2 m copper Cable (channel link) ~10 m of cable to XTRP 24 Linkers 24 Linker Output Modules Neighboring cards connected over backplane

Ben Kilminster 11 Feb 2005; p.24 Cornell JC : CDF XFT Upgrade XFT Upgrade Configuration Ansley trigger cable (220 ft) LVDS 168 TDC from COT axial layers 24 crates Axial Finders 3 crates ~2 m copper Cable (channel link) ~10 m of cable to XTRP 24 Linkers Stereo Finders 24 SLAMs 2 crates ~3m optical Neighboring cards connected over backplane 126 TDC from COT stereo layers New cable (~150ft) Optical Data ~45MHz Data to L2 SLAMs replace Linker Output Modules 2 bin XTC 6 bin XTC 2

Ben Kilminster 11 Feb 2005; p.25 Cornell JC : CDF XFT Upgrade Timing is Tight !

Ben Kilminster 11 Feb 2005; p.26 Cornell JC : CDF XFT Upgrade XTC 2 : Measured start/stop time for each window Consistent with 3ns timing resolution Getting TDC data to XFT  COT data split into two paths: trigger and data  Trigger info is put into 6 time bins by the new XTC2 mezzanine card  Data driven to Stereo Finders by optical fiber link from optical transmitter card to optical receiver card XTC XTC2 TDC Tx Rx XFT Stereo Finder ~150 ft Optical fiber COT Rx card on Finder: Receives optical data Tests show good performance Rx

Ben Kilminster 11 Feb 2005; p.27 Cornell JC : CDF XFT Upgrade Improving the Hit Binning Algorithm  Change binning of hits  6 Bins  Maximized time window intervals to avoid some bins being under-utilized  Better fake rejection than trivial binning: 20%  “Not sure” window  Most hits fire two time bins  ~40ns  Bin width: 24ns  If hit exists in previous bin, ignore hits at beginning of bin (“not sure window”)  Both improvements give an additional ~40% fake rejection compared to no “not-sure” window 24ns Not sure Window 18ns Time Bin N Bin N+1 ASDQ Threshold

Ben Kilminster 11 Feb 2005; p.28 Cornell JC : CDF XFT Upgrade Improving Segment Finding Patterns  New Finder Chips  Driving factor in chip choice  7 times more “masks” == unique segment patterns from track simulation Segment Finder Chips 2 Time Bins, masks 6 Time Bins, Masks Finder Axial SL Finder Axial SL Finder Axial SL Finder Axial SL Segment Finder Chips ImplementationLogic Elements Used Speed Stereo Layer 4 6 bins Flex 10K502,500 / 2,880 87% used 16.5 ns Axial Layer 4 2 bins Stratix 2S6010,602 / 48,352 22% used 33 ns

Ben Kilminster 11 Feb 2005; p.29 Cornell JC : CDF XFT Upgrade Output Stereo- confirmed Tracks A look at the SLAM Board (OSU responsibility) Optical IO VME Interface (Control Code, and State machine interface) SLAM Chip Clock Gen/Dist Design Storage Linker Input Tracks Stereo Finder Segments

Ben Kilminster 11 Feb 2005; p.30 Cornell JC : CDF XFT Upgrade Impact on A Specific Trigger  Scenario C Two-Track Trigger Lumi [1E32 cm -2 s -1 ] Bin  [mb] Using 6-Bin Stereo  [mb] Ratio Luminosity Uses only 2 of 3 Stereo Layers 3x10 32 cm -2 s -1

Ben Kilminster 11 Feb 2005; p.31 Cornell JC : CDF XFT Upgrade Conclusions  Accelerator performance has been excellent  But…high luminosity at 396nsec bunch spacing leads to many interactions/crossing  We need to upgrade the XFT to take advantage of the great opportunity  The XFT Upgrade will meet the needs of high L running  This upgrade gives us the required factor of 3 rejection of fakes  System can be installed and commissioned with little impact on the current XFT  Not all capabilities have been explored  Current rejection only making use of 2 of 3 stereo layers.  Expect another factor of ~2 by using stereo extrapolation in Level 2  Mass triggers are also possible at Level 1 and/or Level 2  Schedule:  Prototypes under design.  Make extensive use of experience from existing system.  Expect completed system in ~15 months  System Operational by Jan 2006.

Ben Kilminster 11 Feb 2005; p.32 Cornell JC : CDF XFT Upgrade BACKUPS

Ben Kilminster 11 Feb 2005; p.33 Cornell JC : CDF XFT Upgrade XFT Data Path  TDC Transition module  Timing and multiplexing  Fiber optic transmit board  Use on: TDC TM, SLAM interface  Fiber optic receiver board  Use on: Finder, L2 Pulsar  Prototypes built and tested  Look good.  Investigating higher data rates  Production runs will await vertical slice test. Optical data Electrical data

Ben Kilminster 11 Feb 2005; p.34 Cornell JC : CDF XFT Upgrade Fibers Used in the XFT Upgrade  Fibers from XTC to Finder  200ft + 2ft breakout each end  Total installation: 38 bundles of 4 fibers + 36 bundles of 6 fibers  Pulling fibers expected to take ~7 days  Will need fibers pulled for commissioning transition boards

Ben Kilminster 11 Feb 2005; p.35 Cornell JC : CDF XFT Upgrade XFT Stereo Finder Board

Ben Kilminster 11 Feb 2005; p.36 Cornell JC : CDF XFT Upgrade Firmware Progress Stereo Chip Compilation  ; Family ; Stratix II  ; Device ; EP2S60F484C3  ; Timing Models ; Preliminary  ; Total ALUTs ; 10,602 / 48,352 ( 21 % )  ; Total pins ; 150 / 335 ( 44 % )  ; Total memory bits ; 33,088 / 2,544,192 ( 1 % )  ; DSP block; 0 / 288 ( 0 % )  ; Total PLLs ; 0 / 6 ( 0 % )  ; Total DLLs ; 0 / 2 ( 0 % ) SLAM Chip Compilation  ; Family ; Stratix  ; Device ; EP1S40F1020C5  ; Timing Models ; Production  ; Total logic elements ; 25,081 / 41,250 ( 60 % )  ; Total pins ; 341 / 782 ( 43 % )  ; Total memory bits ; 6,912 / 3,423,744 ( < 1 % )  ; DSP block; 0 / 112 ( 0 % )  ; Total PLLs ; 1 / 12 ( 8 % )  ; Total DLLs ; 0 / 2 ( 0 % ) Quartus II Version 4.1 Build /29/2004 SJ Full Version The Stereo Finder and SLAM designs make extensive use of reprogrammable devices. l Major progress in firmware over the last 6 months l Functional designs have been implemented l Timing has been studied

Ben Kilminster 11 Feb 2005; p.37 Cornell JC : CDF XFT Upgrade The Axial Finder Chip 140 inputs Mask finding Dead COT wire list L1 and L2 storage Pixel Output Axial Finder: implemented using Altera FLEX 10K70 chip. Stereo Finder: Altera Stratix EP2S60 chip

Ben Kilminster 11 Feb 2005; p.38 Cornell JC : CDF XFT Upgrade Stereo Finder Chip Aligns data from 3 TDC modules wrt 16.5 ns clock To register 6 time bins for 12 cells, requires 24 time slices Data multiplexed to provide 133 bits of information for segment finding in one core cell For each of 8 core cells, finder algorithm is run producing 12 pixels of phi and/or slope output to SLAM module concentration on path to SLAM

Ben Kilminster 11 Feb 2005; p.39 Cornell JC : CDF XFT Upgrade Pixel Driver Chip Pixels from 5 Finder Chips sent through two paths to SLAM Pixel Data from 3 Finder Chips (18 core cells) are accumulated in each FIFO Pixel Data sent to SLAM in two 15° slices containing 18 core cells of pixels for association to axial tracks

Ben Kilminster 11 Feb 2005; p.40 Cornell JC : CDF XFT Upgrade L2 Output Chip demonstration of something which works - can be optimized 32 bits of Pixel data is stored as a slice in the FIFOs, 3 slices per Cell, 8 Cells from each Finder. On L1 Accept, FIFO outputs to multiplexers, then sent to PULSAR board. Otherwise, FIFO slice overwritten. 96 bits per cell * 8 cells per Finder Chip * 4.5 Finder Chips = 3,456 bits per Finder SL7 board 16 bits every 16.5ns, so it will take --> 3,456/16 * 16.5ns = 3.564us

Ben Kilminster 11 Feb 2005; p.41 Cornell JC : CDF XFT Upgrade Cable Reader Latch Pixels Remap Pixels SubRoad Finder Stereo Single Linker L3 pixels All L5 pixels All L7 pixels All L3 pixels 3layers by 3 cables Stereo Single Linker L5 pixels Single Linker L7 pixels Process PtByPhi Array Reformat Linker Linkers 0-5 to Linkers 6-11 to 4 Phi bits by 48 Pt Bits Array Stereo Confirmation SLAM Chip Loop over 12 linkers

Ben Kilminster 11 Feb 2005; p.42 Cornell JC : CDF XFT Upgrade Firmware Progress Stereo Chip Compilation  ; Family ; Stratix II  ; Device ; EP2S60F484C3  ; Timing Models ; Preliminary  ; Total ALUTs ; 10,602 / 48,352 ( 21 % )  ; Total pins ; 150 / 335 ( 44 % )  ; Total memory bits ; 33,088 / 2,544,192 ( 1 % )  ; DSP block; 0 / 288 ( 0 % )  ; Total PLLs ; 0 / 6 ( 0 % )  ; Total DLLs ; 0 / 2 ( 0 % ) SLAM Chip Compilation  ; Family ; Stratix  ; Device ; EP1S40F1020C5  ; Timing Models ; Production  ; Total logic elements ; 25,081 / 41,250 ( 60 % )  ; Total pins ; 341 / 782 ( 43 % )  ; Total memory bits ; 6,912 / 3,423,744 ( < 1 % )  ; DSP block; 0 / 112 ( 0 % )  ; Total PLLs ; 1 / 12 ( 8 % )  ; Total DLLs ; 0 / 2 ( 0 % ) Quartus II Version 4.1 Build /29/2004 SJ Full Version The Stereo Finder and SLAM designs make extensive use of reprogrammable devices. l Major progress in firmware over the last 6 months l Functional designs have been implemented l Timing has been studied

Finder Timing 61 (16.5 ns) clock ticks = 1007 ns from when first TDC data arrives to when output of receiver on SLAM has 18 cells

Ben Kilminster 11 Feb 2005; p.44 Cornell JC : CDF XFT Upgrade Stereo Finder Algorithm  Finder Algorithm  Similar to axial XFT  6 time bins input (72 bits per 12-wire cell) vs 2 time bins(24 bits)  8 12-wire cells vs 4 cells per FPGA  16.5ns clock vs 33ns clock  Much larger Mask set  L2 Pulsar Data(96 bits output)  Implement in newest ALTERA Stratix 2 FPGA

Ben Kilminster 11 Feb 2005; p.45 Cornell JC : CDF XFT Upgrade Segment Finding Algorithm Found pixel phi & slope ! Check 4-wire patterns (generated by simulating tracks) in top, middle, and bottom 4 wires Check all allowed combinations of the three 4-wire- patterns Output 1,2, or 3 misses For each SL (3,5,7), there are 3 designs for each allowed number of misses (1,2,or 3) 2 designs can be loaded: one of the above plus a testing algorithm which allows us to input test vectors and verify output through rest of the system SL