Multi-Level Programmable Array 20023179 Kim, Hyung ock.

Slides:



Advertisements
Similar presentations
Lecture 11-1 FPGA We have finished combinational circuits, and learned registers. Now are ready to see the inside of an FPGA.
Advertisements

1.8 Combinations of Functions: Composite Functions The composition of the functions f and g is “f composed by g of x equals f of g of x”
Prof. Sin-Min Lee Department of Computer Science
Penn ESE534 Spring DeHon 1 ESE534: Computer Organization Day 14: March 19, 2014 Compute 2: Cascades, ALUs, PLAs.
Gate-Level Minimization
MVI Function Review Input X is p -valued variable. Each Input can have Value in Set {0, 1, 2,..., p i-1 } literal over X corresponds to subset of values.
COE 202: Digital Logic Design Combinational Circuits Part 3 Dr. Ahmad Almulhem ahmadsm AT kfupm Phone: Office: Ahmad Almulhem, KFUPM.
ECE 667 Synthesis & Verification - Boolean Functions 1 ECE 667 Spring 2013 ECE 667 Spring 2013 Synthesis and Verification of Digital Circuits Boolean Functions.
Parity. 2 Datasheets TTL:  CMOS: 
EDA (CS286.5b) Day 17 Sequential Logic Synthesis (FSM Optimization)
ECE Synthesis & Verification - Lecture 18 1 ECE 697B (667) Spring 2006 ECE 697B (667) Spring 2006 Synthesis and Verification of Digital Systems Word-level.
Boolean Functions and their Representations
A New Approach to Structural Analysis and Transformation of Networks Alan Mishchenko November 29, 1999.
Lattice Diagrams using Reed-Muller Logic Shim, Hee Jun.
Multiplexer as a Universal Function Generator
Design of Regular Quantum Circuits
Chapter 4 Logic Gates and Boolean Algebra. Introduction Logic gates are the actual physical implementations of the logical operators. These gates form.
 2001 CiesielskiBDD Tutorial1 Decision Diagrams Maciej Ciesielski Electrical & Computer Engineering University of Massachusetts, Amherst, USA
 2000 M. CiesielskiPTL Synthesis1 Synthesis for Pass Transistor Logic Maciej Ciesielski Dept. of Electrical & Computer Engineering University of Massachusetts,
Multiplexer MUX. 2 Multiplexer Multiplexer (Selector)  2 n data inputs,  n control inputs,  1 output  Used to connect 2 n points to a single point.
Penn ESE Spring DeHon 1 ESE (ESE534): Computer Organization Day 12: February 21, 2007 Compute 2: Cascades, ALUs, PLAs.
Propositional Calculus Math Foundations of Computer Science.
Overview Part 2 – Circuit Optimization 2-4 Two-Level Optimization
Figure to-1 Multiplexer and Switch Analog
Decoders and Multiplexers Prof. Sin-Min Lee Department of Computer Science San Jose State University.
Top-down modular design
Module 3.  Binary logic consists of :  logic variables  designated by alphabet letters, e.g. A, B, C… x, y, z, etc.  have ONLY 2 possible values:
1 CHAPTER 4: PART I ARITHMETIC FOR COMPUTERS. 2 The MIPS ALU We’ll be working with the MIPS instruction set architecture –similar to other architectures.
Systems Architecture I1 Propositional Calculus Objective: To provide students with the concepts and techniques from propositional calculus so that they.
Combinational and Sequential Logic Circuits.
1 Fundamentals of Computer Science Propositional Logic (Boolean Algebra)
Combinational Circuit – Arithmetic Circuit
 A _____________________ is any set of ordered pairs that express a relationship.  A _____________________ is a relationship between two variables. This.
WEEK #9 FUNCTIONS OF COMBINATIONAL LOGIC (DECODERS & MUX EXPANSION)
CSET 4650 Field Programmable Logic Devices
1 Lecture 9 Demultiplexers Programmable Logic Devices  Programmable logic array (PLA)  Programmable array logic (PAL)
Combinational Design, Part 3: Functional Blocks
Kuliah Rangkaian Digital Kuliah 6: Blok Pembangun Logika Kombinasional Teknik Komputer Universitas Gunadarma.
Chapter 3 Gate-Level Minimization
1 Lecture 6 BOOLEAN ALGEBRA and GATES Building a 32 bit processor PH 3: B.1-B.5.
Programmable Logic Devices (PLDs)
Mathematical Preliminaries
Abstract To present a novel logic synthesis method to reduce the area of XOR-based logic functions. Idea: To exploit linear dependency between logic sub-
EE207: Digital Systems I, Semester I 2003/2004
Output Grouping Method Based on a Similarity of Boolean Functions Petr Fišer, Pavel Kubalík, Hana Kubátová Czech Technical University in Prague Department.
Binary decision diagrams (BDD’s) Compact representation of a logic function ROBDD’s (reduced ordered BDD’s) are a canonical representation: equivalence.
Chapter # 4: Programmable Logic
DIGITAL SYSTEMS Programmable devices PLA-PAL Rudolf Tracht and A.J. Han Vinck.
1 Multiplexers (Data Selectors) A multiplexer (MUX) is a device that allows several low-speed signals to be sent over one high-speed output line. “Select.
Combinational Circuit Design. Digital Circuits Combinational CircuitsSequential Circuits Output is determined by current values of inputs only. Output.
Programmable logic devices. CS Digital LogicProgrammable Logic Device2 Outline PLAs PALs ROMs.
SYEN 3330 Digital SystemsJung H. Kim Chapter SYEN 3330 Digital Systems Chapter 4 -Part 1.
LECTURE 4 Logic Design. LOGIC DESIGN We already know that the language of the machine is binary – that is, sequences of 1’s and 0’s. But why is this?
Gates AND, OR, NOT NAND, NOR Combinational logic No memory A set of inputs uniquely and unambiguously specifies.
CALTECH CS137 Winter DeHon CS137: Electronic Design Automation Day 17: March 11, 2002 Sequential Optimization (FSM Encoding)
DIGITAL ELECTRONICS. Everything in digital world is based on binary system. Numerically it involves only two symbols 0 or 1. –0 = False = No –1 = True.
CBSSS 2002: DeHon Universal Programming Organization André DeHon Tuesday, June 18, 2002.
LB Logic Block LB Logic Block LB Logic Block LB Logic Block LB Logic Block LB Logic Block LB Logic Block LB Logic Block LB Logic Block S/V block I/O Cell.
Logic Gates Review. Logic Gates OR gate – 1 if either input is 1 – 0 if they both are 0.
Chapter # 4: Programmable Logic
Simplify Radical Expressions Using Properties of Radicals
CS221: Digital Logic Design Combinational Circuits 3
Lecture 9 Logistics Last lecture Today HW3 due Wednesday
Kerntopf Gate and Regular Structures for Symmetric Functions
Lecture 8 Logistics Last lecture Last last lecture Today
Expressions.
SECM - Requirements Concepts Reston Review
Overview Last lecture Timing; Hazards/glitches
ECE 352 Digital System Fundamentals
Presentation transcript:

Multi-Level Programmable Array Kim, Hyung ock

Inroduction o Regular Structures l Why? Easy to P&R( almost no need to P&R ) l Examples n PLA – like n Binary Tree base n Lattice Diagram –Better solution than UAA –UAA is treated as attempt to combine PLA-like and tree-like

Inroduction o This Presentation is composed as following l Intro to Lattice Diagram l MOPS for multiple-out Lattice Diagram l Generalized architecture for MOPS

1. Intro to Lattice Diagram o Chacteristics l Like Tree and similar to BDD. l BDD has combined predecessors if and only if predecessors in the same level is equal. l But Lattice Diagram has always combine neighbor predecessors by some Rule. It occurs repetition of control variables. l Although BDD grows horizontally, Lattice grows vertically by the repetition of variables… l BDD and Lattice Diagram is made of MUX.

1. Intro to Lattice Diagram l Combining Rule n Basic rule is the combining of two predecessors by XOR n n More rule and method are introduced in “LATTICE DIAGRAMS USING REED-MULLER LOGIC” by Perkowski S1S2 P1-2P2-2P2-2P1-1 S1S2 P1-1 P2-2 (a AND P1-2) XOR (a’ AND P2-1) a` a a` a a`a

2. MOPS for multiple-out Lattice o Some problems in Lattice Diagram l Repetition of control variable n It increases vertical depth. n This problem controlled by variable ordering. l In the case of multi-output func n Ordering is not easy to be performed n There is quite waste for one block n And Partitions generate big empty subareas –Not good method, it leads to horizontal growth.

2. MOPS for multiple-out Lattice o Functional Decomposition l Basic conception is to divide function to sub- functions l There are some decomposition methods n AND Decomposition, OR ~, Decomposition with Mux l Multi-output func can be decomposed by symmetric func n Multi-output func can be composed of Boolean operation(AND, OR, EXOR) of symmetric funcs. n Because of no repetition of variable in symmetric func, this method is very nice to reduce vertical depth.

2. MOPS for multiple-out Lattice o What is symmetric func? l All minterms that have same number of ones in their binary number have same value( zero, or one ). l Eg a,bc,dF(a,b,c,d) : It polarity 1111 = S3,

2. MOPS for multiple-out Lattice o MOPS for 4-variables l MOPS is one diagram but it can express all symmetric func which has same polarity n So that reason, it reduces horizontal width compare to partition-method. a b c d S1S2S3S4

2. MOPS for Multiple-out Lattice o Examples of using MOPS l F = (~b XOR ~d) OR ( a XOR c ) OR ( abcd )  It is decomposed to two symmetric functions S3, S4 that have same polarity a,bc,d a b c d S1S2 S3 S4 + F

3.Generalized architecture for MOPS o Every multi-output Boolean func can be decomposed to vector-OR of symmetric func of variable polarity l Each MOPS has same control variable but different polarity l Outputs of two MOPSes are combined in OR plane MOPSpolarity1MOPSpolarity2 OR plane

3.Generalized architecture for MOPS o Every multi-output func with subset SVi, i= 1~k of mutual symmetric variables can be decompsed to serial composition of K MOPS arrays followed by AND/OR plane. l F( SV ) = f1( SV1 ) OR f2( SV2 ) … OR fk( SVk ) l Each fi( SVi ) is symmetric, it can be expressed by one MOPS MOPS1 AND/OR plane MOPS2MOPS3 SV1SV2SV3