Lecture 11 Switching & Forwarding EECS 122 University of California Berkeley

EECS 122Walrand2 TOCTOC: Switching & Forwarding Why? Switching Techniques Switch Characteristics Switch Examples Switch Architectures Summary

EECS 122Walrand3 Direct vs. Switched Networks: Direct Network Limitations: Distance (coordination delay; propagation limitation) Number of hosts (collisions; shared bandwidth; address tables) Single link technology (cannot mix optical, wireless, …) Internetworking: Externality gain at low cost SwitchingSwitching: Why? Single link n links Switches DirectSwitched

EECS 122Walrand4 Circuit-Switching Circuit-Switching (e.g., Telephone net.) Packet-Switching Datagram (e.g., IP, Ethernet) Datagram Virtual Circuits (e.g., MPLS, ATM) Virtual Circuits Source Routing Comparison SwitchingSwitching: Techniques

EECS 122Walrand5 Mechanism: TechniquesTechniques: Circuit-Switching Link divided into fixed, independent circuits Circuit Switch Connection list Time scale: connection (e.g., TDM, WDM) Packets not switched independently (establish circuit before sending data) Dedicated path and resources from source to destination Setup time; low delays and guaranteed resources thereafter Features:

EECS 122Walrand6 Mechanism: TechniquesTechniques: Packet-Switching Whole link shared by all packets Packet Switch Data separated into packets Switching decision (output port) for each individual packet Statistical multiplexing: Sum of peak rates may exceed link bandwidth (as long as mean does not) Features:

EECS 122Walrand7 TechniquesTechniques: PS - Datagram General idea: no connection establishment, but each packet contains enough info to specify destination Switches contain forwarding tables (but no per-connection “state”) Forwarding tables contain info on which outgoing port to use for each destination Two types of addressing: Layer 2 or Layer 3 Layer 2 Layer 3

EECS 122Walrand8 DatagramDatagram: Layer 2 (e.g., Ethernet) Flat address space (no structure) Forwarding table: Exact match of destination L2 address a b c d e f a 1 b 4 c 3 d 2 e 2 f 2 a 1 b 1 c 1 d 2 e 3 f 4 e|b| To From

EECS 122Walrand9 DatagramDatagram: Layer 3 (e.g., IP) L3-network (e.g., IP) Topological structure – match prefix Either fixed prefix length or longest match E.g. 1 E.g. 2 E.g. 3 Fixed Longest Other A B C D A’ C’ B’

EECS 122Walrand10 Fixed Longest Other A B C D A’ C’ B’ DatagramDatagram: Layer 3 (e.g., IP) E.g matches 4 bits at A, 1 at B, 3 at C  A = LPM 4 bits at A’  A’ = EM

EECS 122Walrand11 Fixed Longest Other A B C D A’ C’ B’ DatagramDatagram: Layer 3 (e.g., IP) E.g matches 3 bits at A, 1 at B, 7 at C  C = LPM

EECS 122Walrand12 DatagramDatagram: Layer 3 (e.g., IP) E.g matches 0 bit at A’  B’ 0 bit at B, 0 at C, 2 at D  D = LPM Fixed Longest Other A B C D A’ C’ B’

EECS 122Walrand13 TechniquesTechniques: PS – Virtual Circuit Connection setup establishes a path through switches A virtual circuit ID (VCI) identifies path Uses packet switching, with packets containing VCI VCIs are often indices into per-switch connection tables; change at each hop VC1 VC2 VC1 VC2 VC3 VC2 In, VC Out, VC 1, 1 4, 1 1, 2 4, 3 2, 1 4, 2 ….

EECS 122Walrand14 TechniquesTechniques: Source Routing source Each packet specifies the sequence of routers (or of output ports) from source to destination

EECS 122Walrand15 TechniquesTechniques: Comparison DatagramVirtual circuit switching Circuit switching Forwarding cost highlownone Bandwidth utilization highflexiblelow Resource reservations noneflexibleyes Robustness*highlow *The idea is that in case of failure, circuit and VC are lost; datagram routing can adapt after routing update ….

EECS 122Walrand16 SwitchingSwitching: Characteristics Ports Fast Ethernet, OC-3, ATM, … Protocols ST, Link Agg., VLAN, OSPF, RIP, BGP, VPN, Load Balancing, WRED, WFQ Performance Throughput, Reliability, Power, …

EECS 122Walrand17 SwitchingSwitching: Examples Juniper M160 Cisco “GSR” Cisco “7600” Cisco “catalyst 6500” Extreme “Summit” Foundry “ServerIron”

EECS 122Walrand18 ExamplesExamples: Cisco GSR WAN Router – Large throughput; SONET links Up to 16 line cards at 10 Gbps each Crossbar Fabric Line Cards: 1-port OC-192c 4-port OC48c Many others (ATM, Ethernet, …) Cisco GSR ft 19 ” 2ft

EECS 122Walrand19 ExamplesExamples: Juniper M160 WAN Router – Large throughput; SONET links Crossbar Fabric Line Cards: 1-port OC-192c 4-port OC48c Many others (ATM, Ethernet, …) Juniper M160 3ft 2.5ft 19 ” Capacity: 80Gb/s Power: 2.6kW

EECS 122Walrand20 ExamplesExamples: Cisco 7600 MAN-WAN Router Up to 128 Gbps with Crossbar Fabric 10Mbps – 10Gbps LAN Interfaces OC-3 to OC-48 SONET Interfaces MPLS, WFQ, LLQ, WRED, Traffic Shaping

EECS 122Walrand21 ExamplesExamples: Cisco cat 6500 From LAN to Access 48 to /100 Ethernet Interfaces 10 GE, OC-3, OC-12, OC-48, ATM QoS, ACL Load Balancing; VPN Up to 128Gbps (with crossbar) L4-7 Switching VLAN IP Telephony (E1, T1, inline-power Ethernet) SNMP, RMON

EECS 122Walrand22 ExamplesExamples: Extreme - Summit 48 10/100 ports 2 GE (SX, LX, or LX-70) 17.5Gbps non-blocking 10.1 Mpps Wire speed L2 Wire speed L3 static or RIP OSPF, DVRMP, PIM, …

EECS 122Walrand23 ExamplesExamples: Foundry - ServerIron Server Load Balancing Transparent Cache Switching Firewall Load Balancing Global Server Load Balancing Extended Layer 4-7 functionality including URL-, Cookie-, and SSL Session ID-based switching Secure Network Address Translation (NAT) and Port address translation (PAT)

EECS 122Walrand24 SwitchingSwitching: Architectures Generic Architecture First Generation Second Generation Third Generation Input Functions Output Functions Interconnection Designs OUT IN VOB Combined IN/OUT

EECS 122Walrand25 ArchitecturesArchitectures: Generic Input and output interfaces are connected through an interconnect A interconnect can be implemented by Shared memory  low capacity routers (e.g., PC-based routers) Shared bus  Medium capacity routers Point-to-point (switched) bus  High capacity routers input interfaceoutput interface Inter- connect

EECS 122Walrand26 Route Table CPU Buffer Memory Line Interface MAC Line Interface MAC Line Interface MAC Typically < 0.5Gbps aggregate capacity Limited by rate of shared memory Shared Backplane Line Interface CPU Memory Slide by Nick McKeown ArchitecturesArchitectures: First Generation

EECS 122Walrand27 Route Table CPU Line Card Buffer Memory Line Card MAC Buffer Memory Line Card MAC Buffer Memory Fwding Cache Fwding Cache Fwding Cache MAC Buffer Memory Typically < 5Gb/s aggregate capacity Limited by shared bus Slide by Nick McKeown ArchitecturesArchitectures: Second Generation

EECS 122Walrand28 Line Card MAC Local Buffer Memory CPU Card Line Card MAC Local Buffer Memory Switched Backplane Line Interface CPU Memory Fwding Table Routing Table Fwding Table Typically < 50Gbps aggregate capacity Slide by Nick McKeown ArchitecturesArchitectures: Third Generation

EECS 122Walrand29 ArchitecturesArchitectures: Input Functions Packet forwarding: decide to which output interface to forward each packet based on the information in packet header examine packet header lookup in forwarding table update packet header

EECS 122Walrand30 ArchitecturesArchitectures: Output Functions Buffer management: decide when and which packet to drop Scheduler: decide when and which packet to transmit 1 2 Scheduler Buffer

EECS 122Walrand31 ArchitecturesArchitectures: Output Functions (ct) Packet classification: map each packet to a predefined flow/connection (for datagram forwarding) use to implement more sophisticated services (e.g., QoS) Flow: a subset of packets between any two endpoints in the network 1 2 Scheduler flow 1 flow 2 flow n Classifier Buffer management

EECS 122Walrand32 ArchitecturesArchitectures: Output Queued Only output interfaces store packets Advantage Easy to design algorithms: only one congestion point Disadvantage Requires an output speedup Ro/C = N, where N is the number of interfaces  not feasible for large N input interfaceoutput interface Backplane C RORO

EECS 122Walrand33 ArchitecturesArchitectures: Input Queues Only input interfaces store packets Advantages Easy to build Simple algorithms Disadvantages HOL Blocking In practice: Speedup of 2 suffices input interfaceoutput interface Backplane C RORO

EECS 122Walrand34 Note: Head-of-line Blocking The cell at the head of an input queue cannot be transferred, thus blocking the following cells Output 1 Output 2 Output 3 Input 1 Input 2 Input 3 Cannot be transferred because of output contention Being transferred Cannot be transferred because of HOL blocking

EECS 122Walrand35 ArchitecturesArchitectures: Virtual Output Buffers OUT buffers at each input port Complexity: Matching Problem Full throughput algorithm Good Heuristic Note: Figure from Prof. Varaiya’s notes for EE228b Crossbar

EECS 122Walrand36 VOBVOB: Full Throughput Maximum Weighted Matching: A = 14 B = 11 C = 15 D = 10 B + C > A + D => Serve (B, C)

EECS 122Walrand37 VOBVOB: Good Heuristic – i-SLIP Inputs request permission to send from outputs Outputs grant permissions to inputs (round-robin) Inputs accept permissions (round-robin) RequestGrant Last Grant Last Accept AcceptIter

EECS 122Walrand38 ArchitecturesArchitectures: Combined IN/OUT Both input and output interfaces store packets Advantages Easy to built  Utilization 1 can be achieved with limited input/output speedup (<= 2) Disadvantages Harder to design algorithms  Two congestion points  Need to design flow control input interfaceoutput interface Backplane C RORO

EECS 122Walrand39 Switching needed for big networks Internetworking externality Circuit Packet – VC: QoS possible Packet – Datagram L2: Limited by flat address space L3:  Exact Match: Easy lookup – less efficient  Longest Prefix Match Switch functions: control and data Different Architectures: cost vs. performance SwitchingSwitching: Summary