1. Chen-Nien Tsai 2008/10/16 1 Wireless and Broadband Network Laboratory (WBNLAB) Dept. of CSIE, NTUT

2. Introduction The Architecture of Switches The Evolution in the Architecture of Switches Switch Architecture Classification Buffering Strategies  Output-Buffered Switches  Input-Buffered Switches Scheduling Algorithms (arbitration schemes) PIM, iRRM, iSLIP, DRRM 2008/10/16 2 Wireless and Broadband Network Laboratory (WBNLAB) Dept. of CSIE, NTUT

3. A packet switch is a node used to build a network which utilizes the packet switching paradigm for data communication. ATM switches IP routers The high-speed switching technologies are common to both ATM switches and IP routers. Use a simple term: “switch”. 2008/10/16 3 Wireless and Broadband Network Laboratory (WBNLAB) Dept. of CSIE, NTUT

4. Fixed-length data units are better Time slots concept Higher throughput Simpler hardware design Variable-length packets are usually segmented into fixed-length data units. We call these data units “cell” (not necessarily 53 bytes like ATM cells). 2008/10/16Wireless and Broadband Network Laboratory (WBNLAB) Dept. of CSIE, NTUT 4 Time Time slot

5. Introduction The Architecture of Switches The Evolution in the Architecture of Switches Switch Architecture Classification Buffering Strategies  Output-Buffered Switches  Input-Buffered Switches Scheduling Algorithms (arbitration schemes) PIM, iRRM, iSLIP, DRRM 2008/10/16 5 Wireless and Broadband Network Laboratory (WBNLAB) Dept. of CSIE, NTUT

6. 2008/10/16 6 Wireless and Broadband Network Laboratory (WBNLAB) Dept. of CSIE, NTUT Input PortsOutput Ports Control Functions Datapath Functions

7. Operations that are performed on every datagram. Often implemented in special purpose hardware. Control Functions Operations that are performed relatively infrequently. Implemented in software. System configuration, management, and exchange of routing table information. 2008/10/16 7 Wireless and Broadband Network Laboratory (WBNLAB) Dept. of CSIE, NTUT

8. Bus-based switch with single processor Bus-based switch with multiple processors Switch-based switch with multiple processors Optics Inside a Switch 2008/10/16 8 Wireless and Broadband Network Laboratory (WBNLAB) Dept. of CSIE, NTUT

9. 9 Shared Backplane Line Interface CPU Memory Shared Backplane Routing Table CPU Buffer Memory Line Interface MAC Line Interface MAC Line Interface MAC Typically <0.5Gb/s aggregate capacity A shared central bus and a central CPU/memory Bottlenecks 1. The central CPU must process every packets. 2. Every packet has to traverse twice through the shared bus Packet arrival Shared bus

10. 2008/10/16 10 Routing Table CPU Line Card Buffer Memory Line Card MAC Buffer Memory Line Card MAC Buffer Memory Fwding Cache Fwding Cache Fwding Cache MAC Buffer Memory Typically < 5Gb/s aggregate capacity Packet arrival Local process forwarding Parallelism can increase the system throughput. Each packet traverse the bus once. The central CPU maintain the Routing tables. The shared bus is still a bottleneck. Shared bus Cache update

11. 2008/10/16Wireless and Broadband Network Laboratory (WBNLAB) Dept. of CSIE, NTUT 11 Line Card MAC Local Buffer Memory CPU Card Line Card MAC Local Buffer Memory Switched Fabric Fwding Engine Routing Table Fwding Engine Typically < 50Gb/s aggregate capacity Replacing shared bus with a switched fabric. Multiple packets can be transferred across the fabric simultaneously. Packet arrival Local process forwarding

12. A 16-port IP router, with each port operating at 2.4 Gb/s. If all of the line cards wish to transfer datagrams simultaneously, requiring a backplane with an aggregate bandwidth of 16 x 2.4 Gb/s = 38.4 Gb/s It is impractical to build shared backplanes operating at 38.4 Gb/s. 2008/10/16 12 Wireless and Broadband Network Laboratory (WBNLAB) Dept. of CSIE, NTUT

13. 2008/10/16Wireless and Broadband Network Laboratory (WBNLAB) Dept. of CSIE, NTUT 13 Switch Core Line cards Optical links 0.72 Tbps 0.3 - 10Tb/s or higher routers in development OC 768 (39.81 Gbps)

14. Introduction The Architecture of Switches The Evolution in the Architecture of Switches Switch Architecture Classification Buffering Strategies  Output-Buffered Switches  Input-Buffered Switches Scheduling Algorithms PIM, iRRM, iSLIP, DRRM 2008/10/16 14 Wireless and Broadband Network Laboratory (WBNLAB) Dept. of CSIE, NTUT

15. Switches can be classified according to Switching techniques  Time-Division Switching  Space-Division Switching Buffering strategies  Input-Buffered Switches  Output-Buffered Switches  Virtual-Output-Queueing Switches 2008/10/16 15 Wireless and Broadband Network Laboratory (WBNLAB) Dept. of CSIE, NTUT

16. 2008/10/16 16 Wireless and Broadband Network Laboratory (WBNLAB) Dept. of CSIE, NTUT

17. A single internal communication structure Shared by all cells traveling from input to output. Can be a bus, a ring, or a memory. Advantage Can easily be extended to support multicast/broadcast operations. Disadvantage Capacity limitation of the internal communication structure. 2008/10/16 17 Wireless and Broadband Network Laboratory (WBNLAB) Dept. of CSIE, NTUT

18. Multiple physical paths are provided These paths operate concurrently Multiple cells can be transmitted simultaneously Advantage High capacity Disadvantage Internal link blocking may occur 2008/10/16 18 Wireless and Broadband Network Laboratory (WBNLAB) Dept. of CSIE, NTUT

19. 2008/10/16 19 Wireless and Broadband Network Laboratory (WBNLAB) Dept. of CSIE, NTUT

20. 2008/10/16 20 Wireless and Broadband Network Laboratory (WBNLAB) Dept. of CSIE, NTUT

21. Advantages 1. Internally nonblocking  A path is always available to connect an idle input port to an idle output port. 2. Simple in architecture 3. Modular Disadvantage 1. Need N 2 crosspoints 2008/10/16Wireless and Broadband Network Laboratory (WBNLAB) Dept. of CSIE, NTUT 21

22. Introduction The Architecture of Switches The Evolution in the Architecture of Switches Switch Architecture Classification Buffering Strategies  Output-Buffered Switches  Input-Buffered Switches Scheduling Algorithms PIM, iRRM, iSLIP, DRRM 2008/10/16 22 Wireless and Broadband Network Laboratory (WBNLAB) Dept. of CSIE, NTUT

23. Switches need buffers because Store and forward Internal link blocking Output port contention Buffers are required to be placed somewhere in the switches to delay packet for not to drop them. 2008/10/16Wireless and Broadband Network Laboratory (WBNLAB) Dept. of CSIE, NTUT 23 collision delayed Input 1 Input 2 Output 1

24. 2008/10/16Wireless and Broadband Network Laboratory (WBNLAB) Dept. of CSIE, NTUT 24 Switch Fabric (nonblocking)

25. 2008/10/16 25 Wireless and Broadband Network Laboratory (WBNLAB) Dept. of CSIE, NTUT

26. 2008/10/16 26 Wireless and Broadband Network Laboratory (WBNLAB) Dept. of CSIE, NTUT

27. Most early-date research has focused on this architecture. Initial demand of switch capacity is low.  A few to 10-20 Gbit/s 100% throughput Easier to obtain delay bound.  M/D/1 queue What if we need more capacity… 2008/10/16 27 Wireless and Broadband Network Laboratory (WBNLAB) Dept. of CSIE, NTUT

28. Assume A 24-port ATM switch, with each port operating at 2.4 Gb/s. The backplane is fast enough An ATM cell is 53 bytes-long Transmission time is about 177 ns Memory access time is 10 ns If multiple cells are routed to the same output … Store multiple cells in the output buffer per 177 ns. The output buffer could not receive all cells. 2008/10/16 28 Wireless and Broadband Network Laboratory (WBNLAB) Dept. of CSIE, NTUT

29. To build larger-scale and higher-speed switches. Two main problems: Throughput limitation due to the head-of-line (HOL) blocking.  Only 58.6% throughput can be achieved. The need of arbitrating cells due to output port contention.  More difficult to obtain delay bound. 2008/10/16 29 Wireless and Broadband Network Laboratory (WBNLAB) Dept. of CSIE, NTUT

30. Packets destined for other output ports that are free may be blocked. 2008/10/16Wireless and Broadband Network Laboratory (WBNLAB) Dept. of CSIE, NTUT 30

31. 2008/10/16 31 Wireless and Broadband Network Laboratory (WBNLAB) Dept. of CSIE, NTUT

32. An input may have cells granted access by more than one output. Each input can transfer only one cell a time. Other cells have to wait, and their corresponding outputs will be idle. 2008/10/16Wireless and Broadband Network Laboratory (WBNLAB) Dept. of CSIE, NTUT 32 InputOutput 11 22 33 44 InputOutput 11 22 33 44 InputOutput 11 22 33 44 Idle RequestTransferGrand Multiple grants Can’t transfer since no grant received

33. The inefficiency of idle output can be alleviated if the scheduling algorithm runs iteratively. Parallel Iterative Matching (PIM) Iterative Round-Robin Matching (iRRM) Iterative Round-Robin with SLIP (iSLIP) Dual Round-Robin Matching (DRRM) They are VOQ-based algorithms and assume nonblocking switch is used (crossbar switch). 2008/10/16Wireless and Broadband Network Laboratory (WBNLAB) Dept. of CSIE, NTUT 33

34. Three Steps for each iteration 1. Request  Each unmatched input sends a request to every output for which it has a queued cell. 2. Grant  If an unmatched output receives multiple requests, it grants one by randomly selecting a request. 3. Accept  If an input receives multiple grants, it accepts one by randomly selecting an output. 2008/10/16Wireless and Broadband Network Laboratory (WBNLAB) Dept. of CSIE, NTUT 34

35. 2008/10/16Wireless and Broadband Network Laboratory (WBNLAB) Dept. of CSIE, NTUT 35 InputOutput 11 22 33 44 InputOutput 11 22 33 44 InputOutput 11 22 33 44 RequestAcceptGrand Iteration 1 InputOutput 11 22 33 44 InputOutput 11 22 33 44 InputOutput 11 22 33 44 RequestAcceptGrand Iteration 2

36. 1. It is difficult and expensive to implement random function at high speed. 2. PIM could lead to unfairness between connections. 3. PIM does not perform well for a single iteration. (63% throughput) 2008/10/16Wireless and Broadband Network Laboratory (WBNLAB) Dept. of CSIE, NTUT 36 λ 1,1 = 1 λ 1,2 = 1 λ 2,1 = 1 μ 1,1 = 1/4 μ 1,2 = 3/4 μ 2,1 = 3/4 Both input 1 and output 1 select flow 1 with 1/2 probability, resulting in the ¼ departure rate. Flow 1 Flow 2 Flow 3 2 grants2 requests

37. Works similarly to PIM, but uses the round- robin schedulers instead of random selection. Simple to implement. Performs fairly. Two round-robin scheduler (pointers) Accept pointer a i at input i. Grant pointer g j at output j. 2008/10/16Wireless and Broadband Network Laboratory (WBNLAB) Dept. of CSIE, NTUT 37

38. 1. Request Each unmatched input sends a request to every output for which it has a queued cell. 2008/10/16Wireless and Broadband Network Laboratory (WBNLAB) Dept. of CSIE, NTUT 38

39. 2. Grant If an unmatched output receives multiple requests, it chooses one that appears next in its round-robin schedule. The pointer g j is incremented to one location beyond the granted input. 2008/10/16Wireless and Broadband Network Laboratory (WBNLAB) Dept. of CSIE, NTUT 39 Output 2 received two requests (Input 1 & 3)

40. 3. Accept If an input receives multiple grants, it accepts one that appears next in its round-robin schedule. The pointer a i is incremented to one location beyond the accepted output. 2008/10/16Wireless and Broadband Network Laboratory (WBNLAB) Dept. of CSIE, NTUT 40 Input 1 received two grants (output 1 & 2)

41. 1. Does not perform well for a single iteration. 2008/10/16Wireless and Broadband Network Laboratory (WBNLAB) Dept. of CSIE, NTUT 41 16 x 16 switch

42. Works similarly to iRRM, but the difference is that the grant pointers update their positions only if their grants are accepted. 100% throughput with one iteration. Desynchronization effect. 2008/10/16Wireless and Broadband Network Laboratory (WBNLAB) Dept. of CSIE, NTUT 42

43. 1. Request 2008/10/16Wireless and Broadband Network Laboratory (WBNLAB) Dept. of CSIE, NTUT 43

44. 2. Grant If an unmatched output receives multiple requests, it chooses one that appears next in its round-robin schedule. 2008/10/16Wireless and Broadband Network Laboratory (WBNLAB) Dept. of CSIE, NTUT 44 No grant pointers are updated

45. 3. Accept If an input receives multiple grants, it accepts one that appears next in its round-robin schedule. The pointer a j is incremented to one location beyond the accepted output. The accept pointers are updated only in the first iteration. 4. Update Grant pointer The grant pointer g i is is incremented to one location beyond the granted input if and only if the grant is accepted in step 3. The grant pointers are updated only in the first iteration. 2008/10/16Wireless and Broadband Network Laboratory (WBNLAB) Dept. of CSIE, NTUT 45

46. 2008/10/16Wireless and Broadband Network Laboratory (WBNLAB) Dept. of CSIE, NTUT 46 Update grant points after the grant is accepted

47. 2008/10/16Wireless and Broadband Network Laboratory (WBNLAB) Dept. of CSIE, NTUT 47 iSLIP achieves 100% throughput 16 x 16 switches One iteration

48. Main concept When a successful matched, output arbiter moves its pointer to one position beyond the granted input, it must be the only output that moves it pointer to that position. 2008/10/16Wireless and Broadband Network Laboratory (WBNLAB) Dept. of CSIE, NTUT 48 Both inputs request both outputs. The grant arbiter of output 1 will grant to input 1. In the next time slots, outputs no long contend. 11 2 2 1 2 1 2 11 22 11 2 2 1 2 1 2 11 22

49. 1. Each input arbiter performs request selection. 2. Sends a request to the output arbiters. Input arbiters update their pointer values. 3. Each output arbiter performs grant arbitration. Output arbiters update their pointer values. 4. The output arbiters send grant signals to input arbiters. 2008/10/16Wireless and Broadband Network Laboratory (WBNLAB) Dept. of CSIE, NTUT 49

50. 2008/10/16Wireless and Broadband Network Laboratory (WBNLAB) Dept. of CSIE, NTUT 50

51. Smaller arbitration time than iSLIP, while achieving comparable performance. 2008/10/16Wireless and Broadband Network Laboratory (WBNLAB) Dept. of CSIE, NTUT 51

52. 2008/10/16Wireless and Broadband Network Laboratory (WBNLAB) Dept. of CSIE, NTUT 52 Buffer Strategies Output- Buffered Switch Input- Buffered Switch PIM iRRM iSLIP DRRM 100% throughput and good memory utilization Capacity limitation Arbitrating VOQ HOL blocking Difficult to implement, unfair Not perform well with one iteration Smaller arbitration time Scheduling Algorithms Switch Architecture

53. Shared-Memory Switches Banyan-Based Switches Clos-Network Switches Optical Packet Switches IP Route Lookups 2008/10/16Wireless and Broadband Network Laboratory (WBNLAB) Dept. of CSIE, NTUT 53

54. Scheduling Algorithm (arbitration schemes) 1. T. E. Anderson, S. S. Owicki, J. B. Saxe, and C. P. Thacker, "High- speed switch scheduling for local-area networks," ACM Trans. Comput. Syst., vol. 11, no. 4, pp. 319-352, 1993. (PIM) 2. N. McKeown, P. Varaiya, and J. Walrand, "Scheduling cells in an input-queued switch," IEEE Electronics Letters, vol. 29, no. 25, pp. 2174-2175, 1993. (iRRM) 3. N. McKeown, "The iSLIP scheduling algorithm for input-queued switches," IEEE/ACM Transactions on Networking, vol. 7, no. 2, pp. 188-201, 1999. (iSLIP) 4. H. J. Chao and J. Park, "Centralized contention resolution schemes for a large-capacity optical ATM switch," Proc. IEEE ATM Workshop, pp. 11-16, 1998. (DRRM) 2008/10/16Wireless and Broadband Network Laboratory (WBNLAB) Dept. of CSIE, NTUT 54

55. General Introduction 1. N. McKeown, "A Fast Switched Backplane for a Gigabit Switched Router," Business Communication Review, vol. 27, no. 12, 1997. 2. H. J. Chao, C. H. Lam, and E. Oki, Broadband Packet Switching Technologies – A Practical Guide to ATM Switches and IP Routers, John Wiley & Sons Inc., 2001. 3. F. Chang, New Generation Backbone Router - A Longevous Solution, available at http://tp2rc.tanet.edu.tw/ppt/91sem/NGRouterSolution.ppt 4. Kai-Wei Ke, An Introduction to Switches and Routers, CCN Lectures Notes. 2008/10/16Wireless and Broadband Network Laboratory (WBNLAB) Dept. of CSIE, NTUT 55

56. 2008/10/16Wireless and Broadband Network Laboratory (WBNLAB) Dept. of CSIE, NTUT 56

57. 2008/10/16Wireless and Broadband Network Laboratory (WBNLAB) Dept. of CSIE, NTUT 57

58. 1996199820002002 100% 1,000% 10,000% 100,000% DWDM Link speed x2/8 months Internet Traffic x2/1 yr Router capacity x2.2/18 m Moore’s law x2/18 m DRAM access rate x1.1/18 m Source: SPEC95Int & David Miller, Stanford. To prevent routers from being the bottleneck 2008/10/16 58 Wireless and Broadband Network Laboratory (WBNLAB) Dept. of CSIE, NTUT

59. 2008/10/16Wireless and Broadband Network Laboratory (WBNLAB) Dept. of CSIE, NTUT 59

60. Multiple CPUs process packets in parallel. Parallelism can increase the system throughput. 2008/10/16 60 Wireless and Broadband Network Laboratory (WBNLAB) Dept. of CSIE, NTUT Make forwarding decisions

61. Placing a separate CPU at each interface. Each packet traverse the bus once. The central CPU maintain the forwarding tables. Make forwarding decisions 2008/10/16 61 Wireless and Broadband Network Laboratory (WBNLAB) Dept. of CSIE, NTUT

62. Multiple packets can be transferred across the backplane. Switched fabric 2008/10/16 62 Wireless and Broadband Network Laboratory (WBNLAB) Dept. of CSIE, NTUT Make forwarding decisions

63. The Forwarding Decision Destination address parsing Forwarding table lookup Modifying packet header (TTL, checksum, etc.) The Backplane (fabric) Forward datagram to outgoing port. The Output-link Scheduler The datagram waits for its turn to be transmitted on the output link. FIFO queue or other advanced algorithm. 2008/10/16 63 Wireless and Broadband Network Laboratory (WBNLAB) Dept. of CSIE, NTUT

64. Main concept When a successful matched, output arbiter moves its pointer to one position beyond the granted input, it must be the only output that moves it pointer to that position. 2008/10/16Wireless and Broadband Network Laboratory (WBNLAB) Dept. of CSIE, NTUT 64

65. Commercial DRAM x1.1/18 m Moore’s law x2/18 m Router capacity x2.2/18 m DWDM Link speed x2/8 months Access Time (ns) Source: Nick McKeown, Stanford. 2008/10/16 65 Wireless and Broadband Network Laboratory (WBNLAB) Dept. of CSIE, NTUT

66. FIFO Buffer 2008/10/16 66 Wireless and Broadband Network Laboratory (WBNLAB) Dept. of CSIE, NTUT Input Ports Output Ports

67. A time slot is divided into N mini-slots. During each mini-slot, a cell from an input is broadcast to all output ports. Each address filter will decide if the cell should be stored in the following FIFO. 2008/10/16 67 Wireless and Broadband Network Laboratory (WBNLAB) Dept. of CSIE, NTUT

68. Advantage 1. Easy to support multicasting Disadvantages 1. The medium may be congested. 2. High speed shared medium is difficult to design. 3. Memory speed may limit the switch size. 4. Lack of memory sharing among FIFO buffers. To overcome the 4 th disadvantage Shared-Memory Switch 2008/10/16 68 Wireless and Broadband Network Laboratory (WBNLAB) Dept. of CSIE, NTUT

69. 2008/10/16 69 Wireless and Broadband Network Laboratory (WBNLAB) Dept. of CSIE, NTUT Input Ports Output Ports

70. Incoming cells are time-division multiplexed into a single data stream and sequentially written to the shared memory. The routing of cells is accomplished by extracting stored cells to form a single output data stream. The output data stream is demultiplexed into several outgoing lines. 2008/10/16 70 Wireless and Broadband Network Laboratory (WBNLAB) Dept. of CSIE, NTUT

71. Advantage 1. Easy to support multicasting 2. Better memory utilization Disadvantages 1. The medium may be congested. 2. High speed shared medium is difficult to design. 3. Memory speed may limit the switch size. 4. The control in the switches is more complicated. 2008/10/16 71 Wireless and Broadband Network Laboratory (WBNLAB) Dept. of CSIE, NTUT

72. Crossbar-based switches Fully interconnected switches Banyan-based switches 2008/10/16 72 Wireless and Broadband Network Laboratory (WBNLAB) Dept. of CSIE, NTUT FeaturesCrossbar-based Fully interconnected Banyan-based Nonblocking Yes No Self routing YesNoYes Complexity N2N2 N2N2 NlogN

73. 2008/10/16 73 Wireless and Broadband Network Laboratory (WBNLAB) Dept. of CSIE, NTUT