© CEA Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEA All rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA FIB/SEM Dual beam : FEI Expida mm FOUP & 200 mm Open Cassette SEM column : Sirion (3 nm resolution) FIB column : Sidewinder (low kV thinning) Beam Chemistries:  Tungsten deposition  SiO 2 deposition  Insulator enhanced etch Nanolift option (TEM sample preparation & transfer) :  ChunkWizard - Omniprobe - TSU X-Ray Analysis (Oxford) TEM : FEI Tecnai G² F20 STWIN TMP Voltage : 200 kV Electron Source : FEG  TEM point resolution : 0.24 nm  TEM line resolution : 0.14 nm  STEM resolution : 0.20 nm 2kx2k GATAN CCD X-Ray Analysis (EDAX) In-line transmission electron microscopy for micro and nanotechnologies R&D V. Delaye, F. Andrieu, F. Aussenac, O. Faynot, R. Truche, C. Carabasse, A. L. Foucher, A. Danel CEA-LETI, MINATEC, 17 rue des Martyrs, Grenoble Cedex 9 France Phone: +33 (0) Introduction Advanced microelectronics, micro and nanotechnologies characterizations needs :  Reduced cycle time (cost)  High resolution imaging and analysis of materials and structures with nanometers dimensions An adapted tool is Transmission electron microscope (TEM), but :  Dedicated for off-line laboratories  Destructive  Delicate and time consuming sample preparation To meet the needs of such R&D facility, as much in term of cycle time as resolution :  Full 200 and 300 mm wafer FIB-SEM dual beam system for sample preparation (100 nm thick lamella)  200 kV TEM installed close to dual beam and inside cleanroom. 2h30 to 6h00 hours/sample 200 & 300 mm wafers TEM samples In-line TEM resolution The microscope supplier (FEI) specifications are all achieved in dedicated area except for 50Hz (60dB instead of less than 54 dB) acoustic level. However :  Resolution tests in TEM and STEM modes have been successfully conduced with the FEI Tecnai S-Twin 200 kV microscope installed. Preparation to observation flow Starting from wafer loading in the dual beam to TEM picture delivery :  A cycle time between 2h30 and 6h00 hours has been obtained depending on the sample size and the lamella thickness required. This flow includes :  Electron beam assisted tungsten protective layer deposition to reduce surface damage to 1 nm instead of 30 nm with ion beam  Low-kV (5kV) ion beam final thinning for less than 100 nm lamellas (nanometer gate oxide measurement for example) Wafer return for front-end levels An other major concern in R&D and manufacturing semiconductor industry is to reduce wafer costs due to destructive characterization. It has been already shown that sample preparation impact on wafer is limited to 1 mm around the FIB crater; such impact allows the industry (1) to re-introduce wafers after TEM sample extraction at back-end levels. Dedicated TEM area inside the cleanroom :  Anti-vibration TMC table  Acoustical walls  Adapted lighting conditions  Adapted air conditioning flows  Magnetic field canceling system Time management for a 5x5x0.1µm lamella NMOSL1B PTGL250 To go further, we made 2 samples extractions (common gate pattern NMOSL1B L=70nm and isolated transistor PTGL25 W=50nm) at 3 front-end process levels on two FDSOI (Fully Depleted SOI) wafers to study the impact on electrical performances. The device extraction does not affect the electrical performance of all the devices further than 500 µm (from another pattern in the same die).  On NMOSL1B common gate pattern, devices of the whole pattern are completely scrapped.  On PTGL250 isolated transistors other devices, from 180 to 400 µm, on the same pattern work (even if, with degraded performance) except for Step 2. This new result confirms the localized impact of a FIB extraction around the crater for advanced front-end levels. Wafer mapping (11 e-beam dies) Die description with the 2 localized patterns SEM image from isolated PTGL250 transistors pattern with FIB crater zoom Electrical tests results 0.14 nm line resolution HR-TEM Si 110 HR-STEM Si 110 Chunk millingProbe welding Chunk lift-out FIB crater Transfer to gridChunk approach Sample preparation to observation flow example Chunk view Thinned chunk FIB sample preparation Sample transfer TEM analysis Inline TEM Dedicated Cleanroom Area 200 & 300 mm Lots wafers TEM sample preparation using FIB/SEM DualBeam TEM/STEM sample imaging and EDX (1 st analysis) PTGL250 transistors : Voltage threshold PTGL250 transistors : Transconductance FDSOI Transistor FIB/SEMTEM Metal gate > 500µm< 500µm Conclusion :  No measured impact die to die  Reduced impact within a pattern, but depending on following process step  200 and 300 mm wafers can be re-introduced within the process flow Applications : step by step analysis, process monitoring, defectivity. ACKNOWLEDGMENTS : The authors would like to thank FEI Company for assistance and support. This work has been carried out, in the frame of CEA-LETI / ALLIANCE collaboration and STMicroelectronics. REFERENCE : (1) : BICAIS-LEPINAY N. and al., Proceedings of SPIE vol. 6152, 2006.