CPE 731 Advanced Computer Architecture Instruction Set Principles Dr. Gheith Abandah Adapted from the slides of Prof. David Patterson, University of California, Berkeley

6/9/2015CPE 731, ISA 2 Outline Instruction Set Architecture (ISA) Computer Architecture v. Instruction Set Arch. Processor Types ISA Classes How the Architect Can Help the Compiler Writer? MIPS 64

6/9/2015CPE 731, ISA 3 Instruction Set Architecture: Critical Interface instruction set software hardware Properties of a good abstraction –Lasts through many generations (portability) –Used in many different ways (generality) –Provides convenient functionality to higher levels –Permits an efficient implementation at lower levels

6/9/2015CPE 731, ISA 4 Example: MIPS 0 r0 r1 ° r31 PC lo hi Programmable storage 2^32 x bytes 31 x 32-bit GPRs (R0=0) 32 x 32-bit FP regs (paired DP) HI, LO, PC Data types ? Format ? Addressing Modes? Arithmetic logical Add, AddU, Sub, SubU, And, Or, Xor, Nor, SLT, SLTU, AddI, AddIU, SLTI, SLTIU, AndI, OrI, XorI, LUI SLL, SRL, SRA, SLLV, SRLV, SRAV Memory Access LB, LBU, LH, LHU, LW, LWL,LWR SB, SH, SW, SWL, SWR Control J, JAL, JR, JALR BEQ, BNE, BLEZ,BGTZ,BLTZ,BGEZ,BLTZAL,BGEZAL 32-bit instructions on word boundary

6/9/2015CPE 731, ISA 5 Instruction Set Architecture “... the attributes of a [computing] system as seen by the programmer, i.e. the conceptual structure and functional behavior, as distinct from the organization of the data flows and controls the logic design, and the physical implementation.” – Amdahl, Blaauw, and Brooks, 1964SOFTWARE -- Organization of Programmable Storage -- Data Types & Data Structures: Encodings & Representations -- Instruction Formats -- Instruction (or Operation Code) Set -- Modes of Addressing and Accessing Data Items and Instructions -- Exceptional Conditions

6/9/2015CPE 731, ISA 6 Outline Instruction Set Architecture (ISA) Computer Architecture v. Instruction Set Arch. Processor Types ISA Classes How the Architect Can Help the Compiler Writer? MIPS 64

6/9/2015CPE 731, ISA 7 ISA vs. Computer Architecture Old definition of computer architecture = instruction set design –Other aspects of computer design called implementation –Insinuates implementation is uninteresting or less challenging Our view is computer architecture >> ISA Architect’s job much more than instruction set design; technical hurdles today more challenging than those in instruction set design Since instruction set design not where action is, some conclude computer architecture (using old definition) is not where action is –We disagree on conclusion –Agree that ISA not where action is (ISA in CA:AQA 4/e appendix)

6/9/2015CPE 731, ISA 8 Comp. Arch. is an Integrated Approach What really matters is the functioning of the complete system –hardware, runtime system, compiler, operating system, and application –In networking, this is called the “End to End argument” Computer architecture is not just about transistors, individual instructions, or particular implementations –E.g., Original RISC projects replaced complex instructions with a compiler + simple instructions

6/9/2015CPE 731, ISA 9 Computer Architecture is Design and Analysis Architecture is an iterative process: Searching the space of possible designs At all levels of computer systems Creativity Good Ideas Mediocre Ideas Bad Ideas Cost / Performance Analysis

6/9/2015CPE 731, ISA 10 Outline Instruction Set Architecture (ISA) Computer Architecture v. Instruction Set Arch. Processor Types ISA Classes How the Architect Can Help the Compiler Writer? MIPS 64

6/9/2015CPE 731, ISA 11 Processor Types General-Purpose Processors (desktop, server) –Use compilers Special-Purpose Processors (Embedded applications) –Use kernels written in assembly language Reduced Instruction Set Computer (RISC) –MIPS, Power, Alpha Complex Instruction Set Computer (CISC) –80x86, VAX

6/9/2015CPE 731, ISA 12 Outline Instruction Set Architecture (ISA) Computer Architecture v. Instruction Set Arch. Processor Types ISA Classes How the Architect Can Help the Compiler Writer? MIPS 64

6/9/2015CPE 731, ISA 13 ISA Classes

6/9/2015CPE 731, ISA 14 ISA Classes Number of Operands –Zero: Stack »add –One: Accumulator »add B –Two: Register and Memory »add R1, R2 –Three: Register and Memory »add R1, R2, R3 Operands Types –Register-Register (RISC) –Register-Memory (CISC) –Memory-Memory (CISC)

6/9/2015CPE 731, ISA 15 Instruction Encoding

6/9/2015CPE 731, ISA 16 Instruction Encoding: MIPS Example

6/9/2015CPE 731, ISA 17 Addressing Modes Registeradd r1, r3 Immediateaddi r1, 10 Displacementadd r1, 100(r3) Register indirectadd r1, (r3) Indexedadd r1, (r3+r4) Direct or absoluteadd r1, (1000) Memory indirectadd Auto-incrementadd r1, (r3)+ Auto-decrementadd r1, (r3)- Scaledadd r1, 100(r3)[r4] Can the black addressing modes be implemented from the red?

6/9/2015CPE 731, ISA 18 Outline Instruction Set Architecture (ISA) Computer Architecture v. Instruction Set Arch. Processor Types ISA Classes How the Architect Can Help the Compiler Writer? MIPS 64

6/9/2015CPE 731, ISA 19 How the Architect Can Help the Compiler Writer? Compiler optimizations can give orders in magnitude improvement in: –Performance –Code size Can Help by: 1.Provide regularity: operations, registers, addressing modes are orthogonal. 2.Provide Primitives, not solutions (semantic gap) 3.Simplify tradeoffs among alternatives

6/9/2015CPE 731, ISA 20 Outline Instruction Set Architecture (ISA) Computer Architecture v. Instruction Set Arch. Processor Types ISA Classes How the Architect Can Help the Compiler Writer? MIPS 64

6/9/2015CPE 731, ISA 21 MIPS bit GPRr0, r1, r2, … bit FPRf0, f1, f2, … Memory Instructions –LWLDRt, disp(Rs) –SWSDRt, disp(Rs) –L.SL.DFt, disp(Rs) –S.SS.DFt, disp(Rs) Integer Arithmetic Operations –ADDDADDRd, Rs, Rt FP Arithmetic Operations –ADD.SADD.DFd, Fs, Ft –MUL.SMUL.DFd, Fs, Ft