CMS Week Sept 2002 HCAL Data Concentrator Status Report for RUWG and Calibration WG Eric Hazen, Jim Rohlf, Shouxiang Wu Boston University

CMS Week Sept Sept 2002CMS HCAL -- J.Rohlf/E.Hazen2 DCC Engineering Status Six prototype boards working Successful readout of 6 HTRs (144 channels) in test beam through SLink Simple event builder working – FPGA coding for more advanced version underway Final hardware design changes for SLink 64 ready to start

CMS Week Sept Sept 2002CMS HCAL -- J.Rohlf/E.Hazen3 DCC Block Diagram PC-MIP Mezzanine Cards 3 Channel Link Receivers Data from HTR Modules Data Concentrator Logic PMC PCI 33/32 33/64 33/32 to RUI DCC FPGA Universe PCI-VME Bridge S-Link (64) LSC SDRAM TTCRx RJ-45 to aTTS (Fast status)

CMS Week Sept Sept 2002CMS HCAL -- J.Rohlf/E.Hazen4 DCC – Option I Trigger S-LINK DAQ S-LINK FPGA DCC Logic Mezzanine Card Spare Standard PMC Site (33MHz 64 bit) 3x Link Receiver TTCRx FE Data from HTR Cards (LVDS Serial) VME 9Ux400 VME Motherboard (Design ~Frozen) Proposed Transition Module Fast Timing/ Control 235 pin 2mm Connector SCRAPPED

CMS Week Sept Sept 2002CMS HCAL -- J.Rohlf/E.Hazen5 DCC – Option II Spare Standard PMC Site (33MHz 64 bit) 3x Link Receiver TTCRx VME Fast Timing/ Control 235 pin 2mm Connector DAQ S-LINK64 DCC Logic Mezzanine Card FE Data from HTR Cards (LVDS Serial) RJ-45 (10 pin) TTC aTTS DAQ Double-Width VME Module (one backplane slot) All I/O on Front Panel Spare

CMS Week Sept Sept 2002CMS HCAL -- J.Rohlf/E.Hazen6 DCC Development Plans Open issues for DCC logic board: –Readout Link… S-Link64 okay, but what clock speed? Our DCC can only produce 200Mbyte/s. Will run at 66MHz per discussions at CERN –Hard Reset implementation: FPGA reconfiguration but no software re-write of registers? (Not relevant for our case) –TTCrx BGA package required, or may we use mezzanine test board footprint?

CMS Week Sept Sept 2002CMS HCAL -- J.Rohlf/E.Hazen7 DCC Reset Issues ReSync: OK –Clear buffers, reset state machines, etc HardReset: ??? –Reload FPGAs from flash (takes seconds) All flip-flops (internal registers on FPGA) are reset to power-up defaults. CPU must intervene to restore operation –I would expect that this is true for other subsystems? –VME motherboard has VME-PCI bridge …and multiple PCI busses. Resetting these requires full PCI bus re-configuration (by CPU) –Proposal: make ReSync and HardReset identical for our DCC

CMS Week Sept Sept 2002CMS HCAL -- J.Rohlf/E.Hazen8 DCC Development Plans One more logic board prototype: –S-Link(64) output –aTTS outputs (RJ-45) –TTCrx BGA if required Overall Status: –Motherboard and Link Receivers produced Full qty for 32 DCCs plus spares –Final logic board design pending final details…

CMS Week Sept Sept 2002CMS HCAL -- J.Rohlf/E.Hazen9 Proposed VME64x Rules VME64x(P) “Rules” Compliance? –Difficult for us to comply at this late date. –All VME carrier boards have been manufactured. However, most required features exist in our DCC design… See: – Look for Universe II VME 9Ux400 Motherboard Production completed LVDS Link Receiver Production completed DCC Logic Board Final design update underway

CMS Week Sept Sept 2002CMS HCAL -- J.Rohlf/E.Hazen10 Proposed VME64x Rules The “7 Golden Rules” per C.Schwick 1.Implement CR/CSR Space of VME64x –Universe II precludes this but provides own CSR layout 2.Implement the Serial Number –We can do this (but not at “standard” address) 3.…Plug and Play with “address relocation”… –Universe II supports address relocation and slot geographical addressing 4.Do not use dynamic function sizing… –Universe II memory footprint not known until PCI configuration is complete! However, we can use fixed maximum size. 5.Do not use fixed base address –Fine, we don’t 6.Use re-programmable media for CR –CR is hardwired in Universe II 7.All other VME64x features are optional… –We don’t use any (except 3.3V)

CMS Week Sept Sept 2002CMS HCAL -- J.Rohlf/E.Hazen11 Proposed VME64x Rules HCAL DCC Implementation provides functionality similar to VME64x. Plug-and-play is supported, but requires specific software It is unfortunate that we cannot comply exactly with the “rules”, but our hardware is already built!

CMS Week Sept Sept 2002CMS HCAL -- J.Rohlf/E.Hazen12 HCAL HTR Data Format Format for one channel

CMS Week Sept Sept 2002CMS HCAL -- J.Rohlf/E.Hazen13 DCC Output Format Follows Latest RUWG Guidance –Payload format preliminary – for size estimate

CMS Week Sept Sept 2002CMS HCAL -- J.Rohlf/E.Hazen14 DCC Event Size Estimate based on preliminary format –Can be reduced if necessary (contains diagnostic / error info for each datum) PRELIMINARY ~2000