ALICE experiment Detectors –Photon spectrometer –Central tracking detectors ITS, TPC, TRD –Particle identification Data acquisition and trigger

ALICE - general view

In action... Full simulation of ALICE (shown is a 2 0  slice) with Pb-Pb events at max multiplicity For full event:

Point2: Ready to move in!

Point2: The TPC assembly hall

The ALICE Inner Tracking System 6 Layers, three technologies (keep occupancy ~constant ~2%) – Silicon Pixels (0.2 m 2, 9.8 Mchannels) – Silicon Drift (1.3 m 2, 133 kchannels) – Double-sided Strip Strip (4.9 m 2, 2.6 Mchannels) R out =43.6 cm L out =97.6 cm SPD SSD SDD

Tracking in the ITS: PbPb central event,  slice 83 o -87 o - primary vertex - secondary vertices => for Hyperons => for Charm and Beauty - dE/dx for particle identification momenta) - improve TPC momentum resolution - stand-alone tracking for low-P t particles

ALICE Silicon Pixel Detector (SPD) 2mm => 150µm +200µm final ?

19/10/01PR/GS/PG/LHC Pys. & Det., Chia10 ALICE Pixel Chip 50 µm x 425 µm pixel cell 8192 cells: 32 columns x 256 rows Active area: 12.8 x 13.6 mm Mixed signal (analogue, digital) Commercial 0.25µm CMOS process Radiation tolerant design (enclosed gates, guard rings) 13 million transistors 10 MHz clock ~100 µW/channel Prototype works to ALICE specs!

detector final – tender completed, production starts early ‘02 47 detectors pre-production – confirms ~ 70% yield Calibration methods compensate for T variations and inhomogeneity of Si SDD Drift time (25 ns) Anode number t =0 Positions of HV dividers Charge injectors event

FEE final prototype (PASCAL) – design review passed, eng. run 2Q 2002 event buffer prototype (AMBRA) – design review passed, eng. run 2Q 2002 SDD: frontend Preamplifiers Analogue memory ADCs

SDD electronic chain in beam test Test of final detectors + electronics with PS One MIP Noise levels Signal vs. drift distance

R&D essentially complete Detector tender completed –Three companies share the 1800 detector production New, radtol FEE chip prototype works fine – very fast development (<one year) by Strasbourg, only minor adjustments needed – Eng. run first half of 2002 Hybrid design defined RO electronics and controls being finalized NOW: tune production/test/assembly procedures and go into construction SSD

SSD assembly TAB bonding on Al/polyimide flexible microcables Microcables serve as multilayer hybrids Known Good Die principle to be applied Microcables are produced in one of the collaborating institutes (Kharkov, Ukraine) Assembly has been proven in labs and in industry => now setting up the assembly chains (France, Italy, Finland, The Netherlands) to produce the 2000 modules and 72 ladders A similar assembly procedure has been developed for the STAR SSD, involving some of the same groups, and applied to ~ 400 detector modules

I SSD front end chip assembly

II SSD Hybrid assembly

III SSD module assembly

SDD/SSD Supports Carbon ladders SSD (St. Petersburg, Russia) – ~ 80 produced 100% of strip ladders now spares and SDD – next: assembly of ancillary components

TPC layout 510 cm E E 88us GAS VOLUME 88 m 3 DRIFT GAS 90% Ne - 10%CO 2 Readout plane segmentation 18 trapezoidal sectors each covering 20 degrees in azimuth

TPC readout

TPC status: Field Cage Cylinders are fabricated from three 120-degree- ‘panels’ glued together (lashing). Production has started in September 2001 Cylinders are fabricated from three 120-degree- ‘panels’ glued together (lashing). Production has started in September 2001 Hand lay-up of composite structure BEING MANUFACTURED!

TPC status: RO chambers R&D completed, in production – Inner RO Chambers 1/4 production done (GSI, Heidelberg, later Bratislava) – Out. RO Chambers start prod. 1st Q02 In assembly CLOSE-UP ON THE PADS Pad Plane: 5504 pads (4x7.5 mm 2 ) CONNECTOR SIDE

TPC status: electronics Ion tail cancellation performed digitally Commercial ADC integrated on custom digital chip => very substantial saving in power, complexity and $! All being prototyped, engineering runs mid 2002 anode wire pad plane drift region 88  s L1: 5  s 200 Hz PASA ADC Digital Circuit RAM 8 CHIPS x 16 CH / CHIP 8 CHIPS x 16 CH / CHIP CUSTOM IC (CMOS 0.35  m) CUSTOM IC (CMOS 0.25  m ) DETECTOR FEC (Front End Card) CHANNELS (CLOSE TO THE READOUT PLANE) FEC (Front End Card) CHANNELS (CLOSE TO THE READOUT PLANE) PADS 1 MIP = 4.8 fC S/N = 30 : 1 DYNAMIC = 30 MIP CSA SEMI-GAUSS. SHAPER GAIN = 12 mV / fC FWHM = 190 ns 10 BIT < 10 MHz BASELINE CORR. TAIL CANCELL. ZERO SUPPR. MULTI-EVENT MEMORY L2: < 100  s 200 Hz DDL (4096 CH / DDL) Power consumption: < 40 mW / channel Power consumption: < 40 mW / channel gating grid

TPC electronics: ALICE TPCE READOUT CHIP (ALTRO) DIGITAL TAIL CANCELLATION PERFORMANCE ADC counts Time samples (170 ns) Adaptive Baseline Correct. I Adaptive Baseline Correct. I ADC Tail Cancel. Tail Cancel. Data Format. Data Format. Multi-Event Memory Adaptive Baseline Correct. II Adaptive Baseline Correct. II bit 20 MSPS 11- bit CA2 arithmetic 18- bit CA2 arithmetic 11- bit arithmetic 40-bit format 40-bit format SAMPLING CLOCK 20 MHzREADOUT CLOCK 40 MHz DIGITAL PROCESSOR & CONTROL LOGIC 8 ADCs MEMORY 0.25  m (ST) area:64mm 2 power:29 mW / ch SEU protection

Dimuon Spectrometer Study the production of the J/ ,  ', ,  ' and  '' versus the centrality of the reaction Resolution of 70 MeV on the J/  and 100 MeV on the  overall performance improved with updated detector design (TDR addendum) Plot of 1-month Pb run result, showing the good separation of the various resonances, allowing a systematic study of Debye screening The spectrometer is taking shape: –Production of magnet started (yoke and coil) –Trigger chambers final prototype tested in GIF with final electronics –Begin of detector production in 2002 The absorber design is being revised to try to overcome a major cost overrun

Transition Radiation Detector (TRD) main aims: – high p t (> 1 GeV) electron identification – trigger on high p t (>3 GeV) electrons and jets – physics: heavy quarks (c, b), quarkonia (J/Psi, Y), jets detector: – fiber radiator to induce TR (  > 2000) – large (800 m 2 ), high granularity (> 1M ch.) drift detectors – online trigger electronics to select stiff tracks (measure sagitta) x6

TRD

ALICE Photon Spectrometer (PHOS) Physics – Thermal radiation – High p t physics – Tagged jets Detector –Dimensions:  0.12,  100  (1  8 m 2 ) at radius R  4.6 m –PbWO 4 crystals, X 0 = 0.89 cm, int = 19.5 cm, Moliere radius: 2.0 cm –Granularity: 2.2  2.2 cm 2 (  , length: 18 cm –  0 identified from 3 to > 50 GeV/c – Energy resolution 2% above 3 GeV/c Starting pre-production

Forward detectors PMD T0 R 2.6 < |  | < 3.3 T 0 for the TOF (~ 50 ps time res.) Two arrays of 12 quartz counters. Also backup to V0 FMD Measure Multiplicity and  dist. over 1.6 1) V0 1.6 < |  < 3.9 Interaction trigger, centrality trigger and beam- gas rejection. Two arrays of 72 scintillator tiles readout via fibers T0 L

ZN ZP Aim: determination of the impact parameter of the collision by measuring the energy carried by the spectator nucleons Where: hadronic calorimeters at ~ 116 m from IP e.m. calorimeter at ~ 8 m from IP Central events selected with both: -Energy in hadronic calorimeters < E 0 -Energy in e.m. calorimeter >E 1 E0E0 E1E1 E had vs E e.m. ALICE ZDC Calorimeters

PCI MEM CPU RORC LDC/L3CPU NIC L2 Trigger PDS 36 TPC Sectors FEE DDL L1 Trigger Switch Trigger Data Trigger Decisions Detector busy FEEFEE PDSPDSPDS L0 Trigger FEE FEE FEE Trigger Detectors: Micro Channelplate - Zero-Degree Cal. - Muon Trigger Chambers - Transition Radiation Detector RORC PCI MEM CPU RORC LDC/FEDC NIC RORC PCI MEM CPU RORC LDC/FEDC NIC RORC PCI MEM CPU RORC LDC/FEDC NIC PCI MEM CPU RORC LDC/L3CPU NIC FEE PCI MEM CPU RORC LDC/L3CPU NIC PCI MEM CPU RORC LDC/L3CPU NIC PCI MEM CPU RORC LDC/L3CPU NIC FEE PCI MEM CPU RORC LDC/L3CPU NIC PCI MEM CPU RORC LDC/L3CPU NIC PCI MEM CPU RORC LDC/L3CPU NIC RORC PCI MEM CPU RORC LDC/FEDC NIC LDC: Local Data Concentrator; Software running on standard CPU FEDC: Front-End Digital Computer - generic commercial off-the-shelf CPU RORC: ReadOut Receiver Card (PCI based) L3CPU: L3 Processor - generic commercial off-the-shelf CPU GDC: Global Data Concentrator - generic commercial off-the-shelf CPU NIC: Network Interface Card PCI MEM CPU GDC/L3CPU NIC PCI MEM CPU GDC/L3CPU NIC PCI MEM CPU GDC/L3CPU NIC PCI MEM CPU GDC/L3CPU NIC PCI MEM CPU GDC/L3CPU NIC PCI MEM CPU GDC/L3CPU NIC PCI MEM CPU GDC/L3CPU NIC PCI MEM CPU GDC/L3CPU NIC PCI MEM CPU GDC/L3CPU NIC PCI MEM CPU GDC/L3CPU NIC PCI MEM CPU GDC/L3CPU NIC PCI MEM CPU GDC/L3CPU NIC L3/DAQ/Processor Farm Switch Fabric EDM PCI MEM CPU GDC/L3CPU NIC PCI MEM CPU GDC/L3CPU NIC PCI MEM CPU GDC/L3CPU NIC PCI MEM CPU GDC/L3CPU NIC PCI MEM CPU GDC/L3CPU NIC PCI MEM CPU GDC/L3CPU NIC PCI MEM CPU GDC/L3CPU NIC PCI MEM CPU GDC/L3CPU NIC PCI MEM CPU GDC/L3CPU NIC PCI MEM CPU GDC/L3CPU NIC PCI MEM CPU GDC/L3CPU NIC PCI MEM CPU GDC/L3CPU NIC PCI MEM CPU GDC/L3CPU NIC PCI MEM CPU GDC/L3CPU NIC PCI MEM CPU GDC/L3CPU NIC PCI MEM CPU GDC/L3CPU NIC PCI MEM CPU GDC/L3CPU NIC PCI MEM CPU GDC/L3CPU NIC PCI MEM CPU GDC/L3CPU NIC PCI MEM CPU GDC/L3CPU NIC PCI MEM CPU GDC/L3CPU NIC PCI MEM CPU GDC/L3CPU NIC PCI MEM CPU GDC/L3CPU NIC PCI MEM CPU GDC/L3CPU NIC Computer centre Inner Tracking System Muon Tracking Chambers Particle Identification Photon Spectrometer DAQ and Trigger

TPC event (only about 1% is shown)

Data volume and event rate TPC detector data volume = 300 Mbyte/event, data rate = 200 Hz front-end electronics DAQ – event building realtime data compression & pattern recognition PC farm = 1000 clustered SMP permanent storage system bandwidth 60 Gbyte/sec 15 Gbyte/sec < 1.2 Gbyte/sec < 2 Gbyte/sec parallel processing

HLT trigger Trigger rates pt single > 1 GeV/c pt single > 0.8 GeV/c pt pair > 3 GeV/c J/  /event background/event Hz Online track reconstruction: 1) selection of e + e — pairs (ROI) 2) analysis of e + e — pairs (event rejection) HLT system

HLT trigger