Circuit Simulation and Analysis with HSPICE

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Presentation transcript:

Circuit Simulation and Analysis with HSPICE 國研院國家晶片系統設計中心 July - 2005 林棋勝

Product Development Process

Circuit Design Background Circuit/System Design : A procedure to construct a physical structure which is based on a set of basic component, and the constructed structure will provide a desired function at specified time/ time interval under a given working condition. To be Defined Input Stimuli Output Response

What is Simulation Simulation : To predict the Circuit/System Characteristic after manufacturing Foundry Manufacturing ? Depends on the component behavior, simulation categories include : Complexity Capacity Functional simulation Logic/Gate Level Simulation Switch/Transistor Level Simulation Circuit Simulation Device Simulation

Circuit Simulation Background + - IN+ IN- OUT Circuit Structure IN Physical Structure modeling Circuit Simulation Tool f gain Behavior Electrical characteristic I V

An Inverter Gate Circuit Design * The file name : INV.sp .lib ‘./rf018.l' TT MP1 VDD IN OUT VDD pch w=2u l=0.18u MN1 GND IN OUT GND nch w=1u l=0.18u VDD VDD 0 DC 1.8V VIN IN 0 pulse(0V 1.8V 0n 0.1n 0.1n 1n 2n) .OP .TRAN 0.1n 4n .OPTIONS POST .END Type “ hspice INV.sp ” to simulate inverter circuit

Simulation Results of the Inverter Type “ awaves & “ to view the simulation waveforms

Schematic and Layout Views of the Inverter

A 2-Input NAND Gate Circuit Design * The file name : NAND2.sp .lib ‘./rf018.l' TT MP1 VDD A OUT VDD pch w=2u l=0.18u MP2 VDD B OUT VDD pch w=2u l=0.18u MN1 NET1 A OUT GND nch w=2u l=0.18u MN2 GND B NET1 GND nch w=2u l=0.18u VDD VDD 0 DC 1.8V VA A 0 pulse(0V 1.8V 0n 0.1n 0.1n 1n 2n) VB B 0 pulse(0V 1.8V 0n 0.1n 0.1n 2n 4n) .OP .TRAN 0.1n 4n .OPTIONS POST .END

Simulation Results of the 2-input NAND

Schematic and Layout Views of the 2-input NAND

A 2-Input NOR Gate Circuit Design How to design a 2-input NOR Gate Circuit ? * The file name : NOR2.sp .lib ‘./rf018.l' TT . VDD VDD 0 DC 1.8V VA A 0 pulse(0V 1.8V 0n 0.1n 0.1n 1n 2n) VB B 0 pulse(0V 1.8V 0n 0.1n 0.1n 2n 4n) .OP .TRAN 0.1n 4n .OPTIONS POST .END

Simulation Results of the 2-input NOR

Schematic and Layout Views of the 2-input NOR

Lab A 3-input NAND Gate Circuit Design A 3-input NOR Gate Circuit Design

A layout diagram of Memory Circuit

A Micrograph of Memory Chip