1. NAND Gate Truth table To implement the design,
Follow the procedures from
Slides of part A A B
Output 1

2. Schematic – NAND gate

3. Symbol – NAND gate

4. Test bench Circuit – NAND gate
Note: Keep the frequency of V2 twice than V3 to see output efficiently

5. Simulation results – NAND gate
N1 is output; N2 and N3 are inputs

6. Propagation Delay (tP)
When the gate inputs change, the outputs do not change instantaneously
Defined as the latency between a change in the input and a change in the output measured from the 50% point at the input and the 50% point at the output
tPHL – the time it takes for the output to switch from HIGH to LOW
tPLH – the time it takes for the output to switch from LOW to HIGH

7. Analysis
Tabulate the propagation delays (tPHL, tPLH) for NAND gate from the waveform
Use marker and cursor to find out the propagation delay, a little bit similar like Multisim
It will be like 0.6 ns

8. Propagation Delay – NAND (tPLH): Example from Tanner v15
tPLH = 0.6ns

9. Propagation Delay – NAND (tPHL): Example from Tanner v15
tPHL = 0.9ns