MS_uC / dnd / V ARM966E-Mem-JTAG-Clock Programming Microcontroller ARM966E-S specifications: Memory – JTAG - Clock Autumn term K Byte Burst Flash 64K or 96K Byte SRAM 256K or 512K Byte Burst Flash OTP Mem UARTI2CSPI TIMRTC EXT. Bus GPIO USB 2.0FS CAN 2.0B Enet MAC PFQ BC DMA INTR Cntl ARM966 E CORE w/DSP 96 MHz CLK Cntl ADC LVD BOD PLL JTAGETM9

MS_uC / dnd / V ARM966E-Mem-JTAG-Clock ARM966E Benefits vs. ARM7TDMI: Harvard / von Neumann Architecture z 5 stage pipeline reduces Clocks Per Instruction (CPI) F = Fetch D = Decode E = Execute M = Memory Read W = Memory Write-Back zHarvard Architecture improves Load/Store performance zARMv5TE Architecture with DSP Instructions (1-cycle 32x16 MAC, Saturated Math, and others) zTightly Coupled Memories (TCM), more deterministic zAHB and DTCM Write Buffers for less stalls ®

MS_uC / dnd / V ARM966E-Mem-JTAG-Clock What, an ARM9 with no Cache? z STR910 is taking a unique approach to Eliminate the need for Traditional Cache memory, but at the same time… yKeep performance high while executing code directly from Flash memory yKeep interrupt latency low with less jitter yKeep device cost to a minimum yMaintain a single-chip embedded control system zTraditional Instruction Cache memory is not good for real-time embedded control zInterrupt Response Time has a lot of “jitter” zTraditional Cache Memory requires lots of Silicon area …. More Expensive zSome Traditional Cache memory systems rely on external memory devices (Flash, SDRAM) ®

MS_uC / dnd / V ARM966E-Mem-JTAG-Clock STR910 Enhancements of ARM966E z32-bit wide Single-Cycle SRAM z32-bit wide Burst Flash Memory zBurst Memory interface Operates up to 96MHz (10.4 ns) when retrieving Sequential 1-Word Instructions zPre-Fetch Queue (PFQ) and Branch Cache (BC) zPFQ always looks ahead fetching instructions during idle bus cycles zBC remembers last four jumps, immediately loading PFQ upon jump (branch) ®

MS_uC / dnd / V ARM966E-Mem-JTAG-Clock Pre-Fetch Queue and Branch Cache zBC holds 4 instructions for each of 4 most recent branches zBC loads PFQ immediately with all 4 instructions at once into PFQ if branch address matches zPFQ will not stall upon a branch match z5 th BC entry has instructions to read VIC zPFQ will not flush when CPU reads a literal (a constant in instruction memory) What happens when instructions are not sequential? Will PFQ stall? What happens when instructions are not sequential? Will PFQ stall? ®

MS_uC / dnd / V ARM966E-Mem-JTAG-Clock JTAG Specifics zJTAG Interface y5 standard signals (JTDI, JTDO, JTMS, JTCK, JTAG) complying with IEEE specification yAdditional JRTCK (return TCK) xNot required if ARM core clock 10 times JTCK xRequired to pace JTCK if ARM core clock less than 10 times JTCK zIn-System Programming yProgram and erase Main and Second Flash through JTAG yProgram OTP yConfigure STR91xF with software configuration to zBoundary Scan yAll pins except JTAG, Oscillator Inputs and TAMPER_IN zJTAG Debug using ARM EmbeddedICE-RT logic yHalt or Monitor mode y2 breakpoints/watchpoints, run, halt, single step zJTAG Security Bit yWhen set disables all JTAG operations except ‘Full Chip Erase’ JTAG: Joint Test Action Group IEEE : Standard Test Access Port and Boundary-Scan Architecture ®

MS_uC / dnd / V ARM966E-Mem-JTAG-Clock ETM: Enhanced trace module Specifics zEmbedded ETM9 adds additional debug capability yReal-time instruction flow Trace yTrace filtering and triggering zDedicated 9-pin ETM interface in conjunction with JTAG interface yETM interface can be re- used as GPIO once development is finished yExternal Trace Port Analyzer connects to STR91xF through ETM connector and to host PC though USB2.0 or Ethernet yETM connector includes ETM and JTAG signals Lauterbach ®

MS_uC / dnd / V ARM966E-Mem-JTAG-Clock STR910 Memory Map z Single Linear Address Range y4 Gigabyte range yHarvard busses transparent to firmware yCode and data separated in silicon z High Speed Peripherals on AHB z Lower Speed Peripherals on APB yFirmware accesses APB through a bridge, or window, on the AHB z Separate Ranges for Write Buffer yPeripherals have two address ranges yOne for buffered writes and another for non-buffered writes yBuffered writes increase overall performance yNon-buffered writes guarantee data coherency z Dual Flash Bank Memories yMCU can write/erase one while reading other yEither Flash can reside at boot location (address 0x ) yBank order is user defined ®

MS_uC / dnd / V ARM966E-Mem-JTAG-Clock Flexible Clock Management zMaster Clock Control selectable from three sources yMain Oscillator yRTC Clock yPLL zFrom the master clock the CCU generates individually gated and scaled clock sources for yCPU fCPUCLK yAHB fAHBCLK yEMI fEMICLK yUART Baud Generators fBAUD yStandard Timerss fTIM01 and fTIM23 yUSB fUSB zUSB Interface Clock comes from one of three sources yfMSTR at 48MHz yfMSTR at 96MHz with optional divide-by-two yExternal 48 MHz on pin P2.7 zEthernet MAC Clock comes from one of two sources y25 MHz from Main Oscillator (fOSC) output from P5.2 yExternal 25MHz connected to external PHY. ®

MS_uC / dnd / V ARM966E-Mem-JTAG-Clock CCU Operational Example ®

MS_uC / dnd / V ARM966E-Mem-JTAG-Clock Clock Control Unit (CCU) ® UART,... GPIO 7 Examples:

MS_uC / dnd / V ARM966E-Mem-JTAG-Clock If the previous slides were too small... zCheck the ARM 966E-S reference manual ySTR91xF_ARM966_12774.pdf zAnd the STR91xF Reference manual ySTR91xF_Ref-Manual_12126.pdf zThere you will get all the details ®