FPGA Devices & FPGA Design Flow ECE 448 Lecture 5 FPGA Devices & FPGA Design Flow ECE 448 – FPGA and ASIC Design with VHDL

What is an FPGA? Configurable Logic Blocks I/O Blocks Block RAMs ECE 448 – FPGA and ASIC Design with VHDL

Modern FPGA (#Logic resources, #Multipliers/DSP units, #RAM_blocks) Graphics based on The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)

Major FPGA Vendors SRAM-based FPGAs Xilinx, Inc. Altera Corp. Lattice Semiconductor Atmel Flash & antifuse FPGAs Actel Corp. (Microsemi SoC Products Group) Quick Logic Corp. ~ 51% of the market ~ 85% ~ 34% of the market ECE 448 – FPGA and ASIC Design with VHDL

ISE Alliance and Foundation Series Design Software Xilinx Primary products: FPGAs and the associated CAD software Main headquarters in San Jose, CA Fabless* Semiconductor and Software Company UMC (Taiwan) {*Xilinx acquired an equity stake in UMC in 1996} Seiko Epson (Japan) TSMC (Taiwan) Samsung (Korea) Programmable Logic Devices ISE Alliance and Foundation Series Design Software ECE 448 – FPGA and ASIC Design with VHDL

Xilinx FPGA Families Technology Low-cost High-performance 220 nm Virtex 180 nm Spartan II, Spartan IIE 120/150 nm Virtex II, Virtex II Pro 90 nm Spartan 3 Virtex 4 65 nm Virtex 5 45 nm Spartan 6 40 nm Virtex 6 28 nm Artix 7 Virtex 7

Spartan 6 FPGA Family ECE 448 – FPGA and ASIC Design with VHDL

CLB Structure ECE 448 – FPGA and ASIC Design with VHDL

General structure of an FPGA The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) ECE 448 – FPGA and ASIC Design with VHDL

Xilinx Spartan 6 CLB ECE 448 – FPGA and ASIC Design with VHDL

Row & Column Relationship Between CLBs & Slices ECE 448 – FPGA and ASIC Design with VHDL

Three Different Types of Slices 50% 25% 25% ECE 448 – FPGA and ASIC Design with VHDL

Slice X ECE 448 – FPGA and ASIC Design with VHDL

Xilinx Multipurpose LUT (MLUT) 32-bit SR 64 x 1 RAM 64 x 1 ROM (logic) The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)

4-input LUT (Look-Up Table) in the Basic ROM Mode Look-Up tables are primary elements for logic implementation Each LUT can implement any function of 4 inputs ECE 448 – FPGA and ASIC Design with VHDL

6-Input LUT of Spartan 6 ECE 448 – FPGA and ASIC Design with VHDL When the CLB LUT is configured as memory, it can implement 16x1 synchronous RAM. One LUT can implement 16x1 Single-Port RAM. Two LUTs are used to implement 16x1 dual port RAM. The LUTs can be cascaded for desired memory depth and width. The write operation is synchronous. The read operation is asynchronous and can be made synchronous by using the accompanying flip flops of the CLB LUT. The distributed ram is compact and fast which makes it ideal for small ram based functions. ECE 448 – FPGA and ASIC Design with VHDL

When the CLB LUT is configured as memory, it can implement 16x1 synchronous RAM. One LUT can implement 16x1 Single-Port RAM. Two LUTs are used to implement 16x1 dual port RAM. The LUTs can be cascaded for desired memory depth and width. The write operation is synchronous. The read operation is asynchronous and can be made synchronous by using the accompanying flip flops of the CLB LUT. The distributed ram is compact and fast which makes it ideal for small ram based functions.

Reset and Set Configurations No set or reset Synchronous set Synchronous reset Asynchronous set (preset) Asynchronous reset (clear) When the CLB LUT is configured as memory, it can implement 16x1 synchronous RAM. One LUT can implement 16x1 Single-Port RAM. Two LUTs are used to implement 16x1 dual port RAM. The LUTs can be cascaded for desired memory depth and width. The write operation is synchronous. The read operation is asynchronous and can be made synchronous by using the accompanying flip flops of the CLB LUT. The distributed ram is compact and fast which makes it ideal for small ram based functions. ECE 448 – FPGA and ASIC Design with VHDL

MLUT as a 32-bit Shift Register (SRL32) ECE 448 – FPGA and ASIC Design with VHDL

Input/Output Blocks (IOBs) ECE 448 – FPGA and ASIC Design with VHDL

Basic I/O Block Structure Three-State D Q FF Enable EC Three-State Control Clock SR Set/Reset Output D Q FF Enable EC Output Path SR Direct Input FF Enable Input Path Registered Input Q D EC SR ECE 448 – FPGA and ASIC Design with VHDL

IOB Functionality IOB provides interface between the package pins and CLBs Each IOB can work as uni- or bi-directional I/O Outputs can be forced into High Impedance Inputs and outputs can be registered advised for high-performance I/O Inputs can be delayed ECE 448 – FPGA and ASIC Design with VHDL

Clock Management ECE 448 – FPGA and ASIC Design with VHDL

A simple clock tree ECE 448 – FPGA and ASIC Design with VHDL The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) ECE 448 – FPGA and ASIC Design with VHDL

Clock Manager ECE 448 – FPGA and ASIC Design with VHDL The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) ECE 448 – FPGA and ASIC Design with VHDL

Jitter ECE 448 – FPGA and ASIC Design with VHDL The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) ECE 448 – FPGA and ASIC Design with VHDL

Removing Jitter ECE 448 – FPGA and ASIC Design with VHDL The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) ECE 448 – FPGA and ASIC Design with VHDL

Frequency Synthesis ECE 448 – FPGA and ASIC Design with VHDL The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) ECE 448 – FPGA and ASIC Design with VHDL

Phase shifting Figure 4-20 ECE 448 – FPGA and ASIC Design with VHDL The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) Figure 4-20 ECE 448 – FPGA and ASIC Design with VHDL

Clock Management Tiles DCM – Digital Clock Manager PLL - Phase Locked Loop ECE 448 – FPGA and ASIC Design with VHDL

Spartan-6 Family Attributes ECE 448 – FPGA and ASIC Design with VHDL

Spartan-6 FPGA Family Members ECE 448 – FPGA and ASIC Design with VHDL

FPGA device present on the Digilent Nexys 3 board XC6SLX16-CSG324C Size Spartan 6 family 324 pins Logic Optimized Package type (Ball Chip-Scale) Commercial temperature range 0° C – 85° C ECE 448 – FPGA and ASIC Design with VHDL

FPGA Design Flow

FPGA Design process (1) Specification / Pseudocode Design and implement a simple unit permitting to speed up encryption with RC5-similar cipher with fixed key set on 8031 microcontroller. Unlike in the experiment 5, this time your unit has to be able to perform an encryption algorithm by itself, executing 32 rounds….. Specification / Pseudocode On-paper hardware design (Block diagram & ASM chart) VHDL description (Your Source Files) Library IEEE; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity RC5_core is port( clock, reset, encr_decr: in std_logic; data_input: in std_logic_vector(31 downto 0); data_output: out std_logic_vector(31 downto 0); out_full: in std_logic; key_input: in std_logic_vector(31 downto 0); key_read: out std_logic; ); end AES_core; Functional simulation Synthesis Post-synthesis simulation

FPGA Design process (2) Implementation Timing simulation Configuration On chip testing

Tools used in FPGA Design Flow Functionally verified VHDL code Design VHDL code Xilinx XST Synplify Premier Synthesis Netlist Implementation Xilinx ISE Bitstream

Synthesis

Synthesis Tools Xilinx XST Synplify Premier … and others

Logic Synthesis VHDL description Circuit netlist architecture MLU_DATAFLOW of MLU is signal A1:STD_LOGIC; signal B1:STD_LOGIC; signal Y1:STD_LOGIC; signal MUX_0, MUX_1, MUX_2, MUX_3: STD_LOGIC; begin A1<=A when (NEG_A='0') else not A; B1<=B when (NEG_B='0') else not B; Y<=Y1 when (NEG_Y='0') else not Y1; MUX_0<=A1 and B1; MUX_1<=A1 or B1; MUX_2<=A1 xor B1; MUX_3<=A1 xnor B1; with (L1 & L0) select Y1<=MUX_0 when "00", MUX_1 when "01", MUX_2 when "10", MUX_3 when others; end MLU_DATAFLOW;

Circuit netlist (RTL view)

Mapping LUT0 LUT4 LUT1 FF1 LUT5 LUT2 FF2 LUT3

Xilinx XST Inputs/Outputs

Xilinx XST Inputs RTL VHDL and/or Verilog files Constraints – XCF Xilinx constraints file in which you can specify synthesis, timing, and specific implementation constraints that can be propagated to the NGC file. Core files These files can be in either NGC or EDIF format. XST does not modify cores. It uses them to inform area and timing optimization surrounding the cores.

Xilinx XST Outputs NGC Netlist file with constraint information NGR This is a schematic representation of the pre-optimized design shown at the Register Transfer Level (RTL). This representation is in terms of generic symbols, such as adders, multipliers, counters, AND gates, and OR gates, and is generated after the HDL synthesis phase of the synthesis process. LOG This report contains the results from the synthesis run, including area and timing estimation.

RTL view in Synplify Premier General logic structures can be recognized in RTL view comparator incrementer MUX

Crossprobing between RTL view and code Each port, net or block can be chosen by mouse click from the browser or directly from the RTL View By double-clicking on the element its source code can be seen: Reverse crossprobing is also possible: if section of code is marked, appropriate element of RTL View is marked too:

Technology View in Synplify Pro Technology view is a mapped RTL view. It can be seen by pressing button or by double-click on “.srm” file As in case of “RTL View”, buttons can be used here Two additional buttons are enabled: - show critical path - open timing analyst Pay attention: technology view is usually large and presented on number of sheets Technology view is presented using device primitives Ports, nets and blocks browser

Viewing critical path Critical path can be viewed by pressing on Delay values are written near each component of the path

Implementation

Implementation After synthesis the entire implementation process is performed by FPGA vendor tools

Implementation

Translation Circuit Timing Netlist Constraints User Constraint File Synthesis Circuit Netlist Timing Constraints Constraint Editor or Text Editor UCF User Constraint File Translation NGD Native Generic Database file

Mapping LUT0 LUT4 LUT1 FF1 LUT5 LUT2 FF2 LUT3

Placing FPGA CLB SLICES

Routing FPGA Programmable Connections

Configuration Once a design is implemented, you must create a file that the FPGA can understand This file is called a bit stream: a BIT file (.bit extension) The BIT file can be downloaded directly to the FPGA, or can be converted into a PROM file which stores the programming information

Two main stages of the FPGA Design Flow Synthesis Implementation Technology dependent Technology independent RTL Synthesis Map Place & Route Configure Code analysis - Derivation of main logic constructions Technology independent optimization Creation of “RTL View” Mapping of extracted logic structures to device primitives Technology dependent optimization Application of “synthesis constraints” Netlist generation Creation of “Technology View” Placement of generated netlist onto the device Choosing best interconnect structure for the placed design Application of “physical constraints” Bitstream generation Burning device