High performance 110 nm InGaAs/InP DHBTs in dry-etched in-situ refractory emitter contact technology Vibhor Jain, Evan Lobisser, Ashish Baraskar, Brian J Thibeault, Mark Rodwell ECE Department, University of California, Santa Barbara, CA Zach Griffith, Miguel Urteaga Teledyne Scientific & Imaging, Thousand Oaks, CA Sebastian T Bartsch Nanoelectronics Device Laboratory, EPFL, Switzerland D Loubychev, A Snyder, Y Wu, J M Fastenau, W K Liu IQE Inc., 119 Technology Drive, Bethlehem, PA

Outline HBT Scaling Laws Fabrication –Challenges –Process Development DHBT Epitaxial Design Results –DC & RF Measurements Summary 2

Ohmic contacts Lateral scaling Epitaxial scaling Bipolar transistor scaling laws To double cutoff frequencies of a mesa HBT, must: (emitter length L e ) WeWe TbTb TcTc W bc Keep constant all resistances and currents Reduce all capacitances and transit delays by 2 3

InP Bipolar transistor scaling roadmap Emitter Width (nm) 8421 Access ρ (Ω·µm 2 ) Base Contact width (nm) Contact ρ (Ω·µm 2 ) Collector Thickness (nm) Current density mA/µm 2 Breakdown voltage V fτfτ GHz f max GHz Performance Design Evan Lobisser et al, IPRM

Sub-200 nm HBT node: Fabrication Challenges - I Emitter yield drops during base contact, subsequent lift-off steps High stress in emitter metal stack Poor metal adhesion to InGaAs 5 Need for low stress, high yield emitters Fallen emitters

Sub-200 nm HBT node: Fabrication Challenges - II Undercut in emitter semiconductor Helps in Self Aligned Base Liftoff Narrow emitters need controlled semiconductor undercut  Thin semiconductor To prevent short, base metal needs to be thinned  Higher base metal resistance Solution: Undercut in the emitter metal to act as a shadow mask 6 Slow etch plane InP Wet Etch Fast etch plane

Composite Emitter Metal Stack TiW W W/Ti 0.1 W 0.9 metal stack Low stress Refractory metal emitters Vertical dry etch profile W emitter Erik Lind Evan Lobisser TiW emitter 7

Junction Width via SEM, TEM W TiW BC SiN x BCB M1 200 nm 110 nm 100 nm 100 nm emitter metal-semiconductor junction 110 nm emitter-base junction 8

In-situ Emitter Contact Highly doped n-InGaAs regrown on IQE InGaAs and in-situ Mo deposited Active carriers ~ 5×10 19 cm -3 In-situ Mo deposition on n-InGaAs -  c ~ 1.1 .  m 2 * In-situ deposition  repeatable contact resistivity In-situ Mo contacts*  c ~ 1.1 .  m 2 * A. Baraskar et al., J. Vac. Sci. Tech. B, 27, 4,

Process flow Regrown InGaAs emitter cap In-situ Mo dep W/TiW/SiO 2 /Cr dep SF 6 /Ar etch SiN x Sidewall SiO 2 /Cr removal InGaAs Wet Etch Second SiN x Sidewall InP Wet Etch Base Contact Lift-off W/TiW interface acts as shadow mask for base lift off Base and collector formed via lift off and wet etch BCB used to passivate and planarize devices 10 Self-aligned process flow for 110 nm DHBT

Epitaxial Design T(nm)MaterialDoping (cm -3 )Description 10In 0.53 Ga 0.47 As 5  : Si Regrown Cap 10In 0.53 Ga 0.47 As 5  : Si Emitter Cap 10InP 4  : Si Emitter 10InP 1  : Si Emitter 30InP 8  : Si Emitter 25In 0.53 Ga 0.47 As 7-4  : C Base 7.5In 0.53 Ga 0.47 As 9  : Si Setback 15InGaAs / InAlAs 9  : Si B-C Grade 3InP 5  : Si Pulse doping 74.5InP 9  : Si Collector 7.5InP 1  : Si Sub Collector 7.5In 0.53 Ga 0.47 As 2  : Si Sub Collector 300InP 2  : Si Sub Collector SubstrateSI : InP V be = 1 V, V cb = 0.7 V, J e = 0, 30 mA/  m 2 Thin emitter semiconductor  Enables wet etching High collector doping  High Kirk threshold 11

Results - DC Measurements BV ceo = 2.5 J e = 1 kA/cm 2 β = 18 Base ρ sheet = 730 Ω/□, ρ c < 4 Ω·µm 2 Collector ρ sheet = 12 Ω/□, ρ c = 9 Ω·µm f t,f max J e = 23.1 mA/  m 2 P = 41 mW/  m 2 12 Peak f t,f max Gummel plot Common emitter I-V

DUT Short Results - RF Measurements using Off-Wafer LRRM Open G SG Standard Off Wafer LRRM Open & Short Pad Cap Extraction 13 * Koolen et al., IEEE BCTM 1991

1-67 GHz RF Data and Extrapolated Cutoff Frequencies I c = 8.9 mA V ce = 1.74 V J e = 23.1 mA/  m 2 V cb = 0.7 V Single-pole fit to obtain cut-off frequencies 14

Parameter Extraction 15 J kirk = 32 mA/  m 2 cb = 0.7V) C cb /I c = 0.43 psec/V

Equivalent Circuit Hybrid-  equivalent circuit from measured RF data R ex ≈ 3.6  m 2 16

Microstrip Style TRL Calibration Ref Plane for TRL t ~ 1  m h ~ 1  m w ~ 1.7  m BCB AA’ A – A’ Metal 1 Ref Plane set at device edge No further de-embedding required 17 Collector Metal

GHz RF data -20dB/decade fit to obtain cut-off frequencies 18 I c = 9.1 mA V ce = 1.75 V J e = 23.6 mA/  m 2 V cb = 0.7 V

Conclusion Demonstrated smallest junction width for a III-V DHBT (110 nm) Peak f t /f max = 465/660 GHz – J e = 23.6 mA/  m 2 – Power Density (P) = 41 mW/  m 2 High current and power density operation (P > 50 mW/  m 2 ) 19

Questions? Thank You This work was supported by the DARPA THETA program under HR C-0060 and DARPA TFAST under N C A portion of this work was done in the UCSB nanofabrication facility, part of NSF funded NNIN network and MRL Central Facilities supported by the MRSEC Program of the NSF under award No. MR