H. Huang Transparency No.1-1 The 68HC11 Microcontroller Chapter 1: Introduction to 68HC11 The 68HC11 Microcontroller

H. Huang Transparency No.1-2 The 68HC11 Microcontroller

H. Huang Transparency No.1-3 The 68HC11 Microcontroller

H. Huang Transparency No.1-4 The 68HC11 Microcontroller Memory Addressing Memory consists of addressable locations A memory location has 2 components: address and contents Data transfer between CPU and memory involves address bus and data bus CPU memory address bus lines data bus lines Figure 1.5 Data transfer between CPU and memory address contents

H. Huang Transparency No.1-5 The 68HC11 Microcontroller 68HC11 addressing modes Table 1.1 Prefix for number representation BasePrefix binary octal decimal hexadecimal nothing* $ *Note: Some assemblers use &

H. Huang Transparency No.1-6 The 68HC11 Microcontroller ADDRESSING MODES Operands needed in an instruction are specified by one of the 6 addressing modes Immediate mode Direct mode Extended mode Indexed mode Inherent mode Relative mode

H. Huang Transparency No.1-7 The 68HC11 Microcontroller Immediate mode The actual operand is contained in the byte or bytes immediately following the instruction opcode LDAA #22 ADDA LDD #1000 Note that the (#) is a critical assembler directive!

H. Huang Transparency No.1-8 The 68HC11 Microcontroller Direct mode A one-byte value is used as the address of a memory operand (located in on-chip SRAM) ADDA $10 SUBA $20 LDD $30 Extended mode A two-byte value is used as the address of a memory operand LDAA $1000 LDX $1000 ADDD $1030 Indexed mode The sum of one of the index registers and an 8-bit value is used as the address of a memory operand ADDA 10,X LDAA 3,Y

H. Huang Transparency No.1-9 The 68HC11 Microcontroller Inherent mode -Operands are implied by the instruction -No address information is needed ABA INCB INX Relative mode -Used in branch instructions to specify the branch target -Specified using either a 16-bit value or a label (preferred)... BEQ there ADDA #10... thereDECB

H. Huang Transparency No.1-10 The 68HC11 Microcontroller A Sample of 68HC11 Instructions The LOAD instructions A group of instructions that place a value or copy the contents of a memory location (or locations) into a register LDAA Load Accumulator A LDAB Load Accumulator B LDD Load Double Accumulator D LDX Load Index Register X LDY Load Index Register Y LDS Load Stack Pointer can be immediate, direct, extended, or index mode Examples LDAA $10 LDX #$1000

H. Huang Transparency No.1-11 The 68HC11 Microcontroller The ADD instruction A group of instructions perform addition operation ABA ABX ABY ADDA ADDB ADDD ADCA ADCB is specified using immediate, direct, extended, or index mode Examples. ADDA #10 ADDA $20 ADDD $30

H. Huang Transparency No.1-12 The 68HC11 Microcontroller The SUB instruction A group of instructions that perform the subtract operation SBA SUBA SUBB SUBD SBCA ; A  [A] - - C flag SBCB ; A  [B] - - C flag can be immediate, direct, extended, or index mode Examples SUBA #10 SUBA $10 SUBA 0,X SUBD 10,X

H. Huang Transparency No.1-13 The 68HC11 Microcontroller The STORE instruction A group of instructions that store the contents of a register into a memory location or memory locations STAA STAB STD STX STY STS can be direct, extended, or index mode Examples: STAA $20 STAA 10,X STD $10 STD $1000 STD 0,X

H. Huang Transparency No.1-14 The 68HC11 Microcontroller The 68HC11 Machine Code A 68HC11 instruction consists of 1 to 2 bytes of opcode and 0 to 3 bytes of operand information Examples Machine instructions Assembly instruction (in hex format) LDAA # D STAA $ ADDA $02 9B 02 STAA $ INY18 08

H. Huang Transparency No.1-15 The 68HC11 Microcontroller Decoding machine language instructions Procedure Step 1 Compare the first one or two bytes with the opcode table to identify the corresponding assembly mnemonic and format. Step 2 Identify the operand bytes after the opcode field. Step 3 Write down the corresponding assembly instruction. Step 4 Repeat step 1 to 3 until the machine code file is exhausted. A sample of machine codes and assembly instruction format machine code assembly instruction format 01NOP 86LDAA IMM 96LDAA DIR C6LDAB IMM D6LDAB DIR CCLDD IMM DCLDD DIR 8BADDA IMM 9BADDA DIR CBADDB IMM

H. Huang Transparency No.1-16 The 68HC11 Microcontroller DBADDB DIR C3ADDD IMM D3ADDD DIR 97STAA DIR D7STAB DIR DDSTD DIR machine codeassembly instruction format Example. Disassemble the following machine code to its corresponding assembly instructions B Solution: The disassembly process starts from the leftmost byte. We next look up the machine code table to see which instruction it corresponds to. Instruction 1. Step 1. The first byte 96 corresponds to the instruction LDAA DIR. Step 2. The second byte, 30, is the direct address. Step 3. Therefore, the first instruction is LDAA $30.

H. Huang Transparency No.1-17 The 68HC11 Microcontroller Instruction 2. Step 1. The third byte (8B) corresponds to the instruction ADDA IMM. Step 2. The immediate value is 07. Step 3. Therefore, the second instruction is ADDA $07. Instruction 3. Step 1. The fifth byte (97) corresponds to the instruction STAA DIR. Step 2. The DIR address is the next byte 30. Step 3. Therefore, the third instruction is STAA $30. Instruction 4. Step 1. The seventh byte (96) corresponds to the instruction LDAA DIR. Step 2. The DIR value is the next byte 31. Step 3. Therefore, the four instruction is LDAA $31.

H. Huang Transparency No.1-18 The 68HC11 Microcontroller machine code assembly instruction format 01NOP 86LDAA IMM 96LDAA DIR C6LDAB IMM D6LDAB DIR CCLDD IMM DCLDD DIR 8BADDA IMM 9BADDA DIR CBADDB IMM DBADDB DIR C3ADDD IMM D3ADDD DIR 97STAA DIR D7STAB DIR DDSTD DIR

H. Huang Transparency No.1-19 The 68HC11 Microcontroller The 68HC11 Instruction Execution Cycle - Perform a sequence of read cycles to fetch instruction opcode byte and address information. - Optionally perform read cycle(s) required to fetch the memory operand. -Perform the operation specified by the opcode. -Optionally write back the result to a register or a memory location. -Consider the following 3 instructions Assembly instructionMemory locationOpcode LDAA $2000$C000B ADAA $3000$C003BB STAA $2000$C006B

H. Huang Transparency No.1-20 The 68HC11 Microcontroller Instruction LDAA $2000 Step 1. Place the value in PC on the address bus with a request to read the contents of that location. Step 2. The opcode byte $B6 at $C000 is returned to the CPU and PC is incremented by 1.

H. Huang Transparency No.1-21 The 68HC11 Microcontroller Step 3. CPU performs two read cycles to obtain the extended address $2000 from locations $C001 and $C002. At the end the value of PC is incremented to $C003

H. Huang Transparency No.1-22 The 68HC11 Microcontroller Figure 1.12 Instruction 1--execution read cycle Memory contents $19 $37 CPU... $2000 Address bus Data bus $19 $2000 Address $3000 Step 4. The CPU performs another read to get the contents of the memory location at $2000, which is $19. The value $19 will be loaded into accumulator A.