1. Machine Language ELEC 330 Digital Systems Engineering Dr. Ron Hayne

2. 330_022 The 68HC11 Microcomputer  Programming Model Memory Model Microprocessor Model  Internal Computer Operations Instruction Fetch Instruction Execution  Machine Language Programming

3. 330_023 Programming Model  Motorola 68HC11 Microcomputer 7 A 07 B 08-bit Accumulators A & B 15 D 016-bit Double Accumulator D 15 X 0Index Register X 15 Y 0Index Register Y 15 SP 0Stack Pointer 15 PC 0Program Counter SXHINZVCCondition Code Register

4. 330_024 Memory Model 0000    C329B6 C23AC1 C23B33    FFFF22

5. 330_025 Instruction Format  Load Accumulator A LDAA $C200  C100B6  Op Code of LDAA C101C2  Address of Data C10200    C20044  Data number 

6. 330_026 Microprocessor Model  Program Counter  Instruction Register  Accumulators PC IR A B

7. 330_027 Computer Operation  Example Instruction (LDAA) Register and Memory contents  PC C100B6C100 C101C2 IR C10200  A  22  B C2004433 

8. 330_028 Instruction Fetch  PC to Memory as Address Read  PC C100B6C100 C101C2 IR C10200  A  22  B C2004433 

9. 330_029 Instruction Fetch  Memory sends number at address to IR Increment PC  PC C100B6C101 C101C2 IR C10200B6  A  22  B C2004433 

10. 330_0210 Instruction Fetch  PC to Memory as Address Read  PC C100B6C101 C101C2 IR C10200B6  A  22  B C2004433 

11. 330_0211 Instruction Fetch  Memory sends number at address to IR Increment PC  PC C100B6C102 C101C2 IR C10200B6C2  A  22  B C2004433 

12. 330_0212 Instruction Fetch  PC to Memory as Address Read  PC C100B6C102 C101C2 IR C10200B6C2  A  22  B C2004433 

13. 330_0213 Instruction Fetch  Memory sends number at address to IR Increment PC  PC C100B6C103 C101C2 IR C10200B6C200  A  22  B C2004433 

14. 330_0214 Instruction Fetch  Register Contents after Fetch  PC C100B6C103 C101C2 IR C10200B6C200  A  22  B C2004433 

15. 330_0215 Instruction Execution  Data Address to Memory Read  PC C100B6C103 C101C2 IR C10200B6C200  A  22  B C2004433 

16. 330_0216 Instruction Execution  Memory sends data at address to A  PC C100B6C103 C101C2 IR C10200B6C200  A  44  B C2004433 

17. 330_0217 Instruction Execution  Final Register Contents  PC C100B6C103 C101C2 IR C10200B6C200  A  44  B C2004433 

18. 330_0218 Instruction Set Table  Operand hh ll high and low bytes of address Source Form Operation Boolean Expression Machine Code Bytes Op Code Operand ADDAAdd Memory to A A + M  A BBhh ll3 LDAALoad Accumulator A M  A B6hh ll3 STAAStore Accumulator A A  M B7hh ll3 STOPStop Program3F1

19. 330_0219 Machine Language Programming  N1 + N2  SUM  PC LDAAC200B6C200 C201C2 A C2020B ADDAC203BB B C204C2 C2050C STAAC206B7 C207C2N1C20B02 C2080DN2C20C29 STOPC2093FSUMC20DFF C20A 

20. 330_0220 Machine Language Programming  N1 + N2  SUM  PC LDAAC200B6C203 C201C2 A C2020B02 ADDAC203BB B C204C2 C2050C STAAC206B7 C207C2N1C20B02 C2080DN2C20C29 STOPC2093FSUMC20DFF C20A 

21. 330_0221 Machine Language Programming  N1 + N2  SUM  PC LDAAC200B6C206 C201C2 A C2020B2B ADDAC203BB B C204C2 C2050C STAAC206B7 C207C2N1C20B02 C2080DN2C20C29 STOPC2093FSUMC20DFF C20A 

22. 330_0222 Machine Language Programming  N1 + N2  SUM  PC LDAAC200B6C209 C201C2 A C2020B2B ADDAC203BB B C204C2 C2050C STAAC206B7 C207C2N1C20B02 C2080DN2C20C29 STOPC2093FSUMC20D2B C20A 

23. 330_0223 Machine Language Programming  N1 + N2  SUM  PC LDAAC200B6C20A C201C2 A C2020B2B ADDAC203BB B C204C2 C2050C STAAC206B7 C207C2N1C20B02 C2080DN2C20C29 STOPC2093FSUMC20D2B C20A 

24. 330_0224 Summary  Programming Model Memory Model Microprocessor Model  Internal Computer Operations Instruction Fetch Instruction Execution  Machine Language Programming

25. 330_0225 Instructions and Addressing  Addressing Modes Extended Addressing Direct Addressing Inherent Addressing Immediate Addressing Indexed Addressing Relative Addressing

26. 330_0226 Addressing  Effective Address Address formed by microprocessor as part of instruction execution  Addressing Modes Various ways addresses are formed  Memory Map Visual technique for understanding implications of addressing modes

27. 330_0227 Extended Addressing  Complete 16-bit Address of Data  PC LDAAC200B6C200 EXTC201C2 A C2020B ADDAC203BB B EXTC204C2 C2050C STAAC206B7 EXTC207C2N1C20B02 C2080DN2C20C29 STOPC2093FSUMC20DFF C20A 

28. 330_0228 Direct Addressing  Shortened 8-bit Address Most-significant byte 00  Address Range 0000 through 00FF Zero Page Addressing  Shorter and Faster Instructions Use less memory Fetched faster  N1001002 N2001129 SUM0012FF  LDAAC20096 DIRC20110 ADDAC2029B DIRC20311 STAAC20497 DIRC20512 STOPC2063F 

29. 330_0229 Inherent (Implied) Addressing  Some instructions operate on microprocessor registers only No memory address needed  Example ABA A + B  A  N1001002 N2001129 SUM0012FF  LDAAC20096 DIRC20110 LDABC202D6 DIRC20311 ABAC2041B STAAC20597 DIRC20612 STOPC2073F 

30. 330_0230 Double-Byte Data  Some registers hold 16-bit (double-byte) data D, X, Y, SP  Example LDX M:(M+1)  X  Big-endian convention High byte at first (lower) address Low byte at second (higher) address  LDXFE EXTC2 34    X C23456 78 C23578 

31. 330_0231 Immediate Addressing  Constant data placed inside an instruction No memory address Fewer bytes of memory  Data immediately available at end of fetch phase Faster execution  LDAA86 A IMM22    LDXCE X IMM12 34 

32. 330_0232 Indexed Addressing  Op Code and Offset Byte  Effective Address Offset (unsigned) added to Index Register (pointer) Index Register unchanged  Example LDAA 2,X M[2+X]  A  LDAAA6 A INDX0247    C20022 X C20133C200 C20247 C203B7 

33. 330_0233 Relative Addressing  Branch Instructions Make decisions Alter program flow  Condition Code Register Reports test results SXHINZVCCondition Code Register

34. 330_0234 Condition Code Bits  C (Carry) Carry-out from the most-significant bit  V (Overflow) Two’s complement overflow error  Z (Zero) Result contains all zeros  N (Negative) Result is negative  H (Half-carry) Carry from halfway (bit 3) Generally used only with BCD numbers  S, X, I Hardware control bits (later...)

35. 330_0235 Example  ADDA CH 1111 10101010A = N1 +10111100M = N2 01100110A = SUM N xx1x0011CCR SXHINZVC

36. 330_0236 Condition Code Notation  Not all instructions affect all the condition code bits  Always use the instruction set table to determine how the bits work Don’t assume! SymbolOperation -Bit is unaffected by this instruction 0Bit is always cleared to 0 by this instruction 1Bit is always set to 1 by this instruction  Bit is set or cleared depending on instruction

37. 330_0237 Branch Instructions  May alter program flow based on the condition code bits Program Counter  Relative Addressing Signed Offset  Effective Address PC plus Offset Branch Range?  Op Code 27 PC Offset 04xx No Branch     Branch    

38. 330_0238 Branch Not Equal to Zero  BNE Branch if Not = Zero ? Z = 0  Example LDAA N1 LOOP ADDA #-1 BNE LOOP STOP  N1001004  LDAAC20096 DIRC20110 ADDAC2028B IMMC203FF BNEC20426 RELC205FC STOPC2063F C273 

39. 330_0239 Addressing Mode Summary INHERENTOp Code IMMEDIATEOp Code DataData-high Data-low DIRECTOp CodeEffective Address Address-low  00dd EXTENDEDOp CodeEffective Address Address-high  hhll Address-low

40. 330_0240 Addressing Mode Summary INDEXEDOp CodeEffective Address Offset  +   Index Register RELATIVEOp CodeEffective Address Relative offset  +   Program Counter

41. 330_0241 Basic Instructions  Arithmetic and Logic  Load and Store Input and Output  Testing and Branching

42. 330_0242 Programming Model  Motorola 68HC11 Microcomputer 7 A 07 B 08-bit Accumulators A & B 15 D 016-bit Double Accumulator D 15 X 0Index Register X 15 Y 0Index Register Y 15 SP 0Stack Pointer 15 PC 0Program Counter SXHINZVCCondition Code Register

43. 330_0243 Instruction Set Table  Source Form Instruction mnemonic Type of operand (opr)data or data address (rel)relative offset  Operation Short word description  Booelan Expression Detailed description of register transfers  Addressing Mode

44. 330_0244 Instruction Set Table  Op Code Machine code for corresponding addressing mode  Operand ii8-bit immediate data ddlow byte of direct address hh llhigh and low bytes of extended address ffunsigned 8-bit offset for indexed addressing jj kkhigh and low bytes of 16-bit immediate data rrsigned 8-bit relative offset for branch

45. 330_0245 Instruction Set Table  Bytes Number of bytes of memory (op code + operand)  Cycles Number of clock cycles to fetch and execute  Condition Codes SymbolOperation -Bit is unaffected by this instruction 0Bit is always cleared to 0 by this instruction 1Bit is always set to 1 by this instruction  Bit is set or cleared depending on instruction

46. 330_0246 Instruction Set Table Source Form Operation Boolean Expression Addr. Mode Machine Code Bytes Cycles Op Code Op- erand ABXAdd B to X X + 00:B  X INH3A13  ADDA (opr)Add Memory to A A + M  A A IMM A DIR A EXT A IND,X A IND,Y 8B 9B BB AB 18 AB ii dd hh ll ff ff 2232322323 2344523445  CLCClear Carry Bit 0  C INH0C12  LDX (opr)Load Index Register X M:(M + 1)  X X IMM X DIR CE DE jj kk dd 3232 3434

47. 330_0247 Instruction Set Table (cont) Source Form Operation Boolean Expression Condition Codes SXHINZVC ABXAdd B to X X + 00:B  X --------  ADDA (opr)Add Memory to A A + M  A --  -   CLCClear Carry Bit 0  C -------0  LDX (opr)Load Index Register X M:(M + 1)  X ----  0-

48. 330_0248 Arithmetic and Logic  ABA Add B to A  ABX Add B to X  ADDA, ADDB, ADDD Add memory to accumulator  ADCA, ADCB Add memory with carry to accumulator

49. 330_0249 Arithmetic and Logic  DEC, DECA, DECB Decrement memory or accumulator  DEX Decrement X  INC, INCA, INCB Increment memory or accumulator  INX Increment X

50. 330_0250 Arithmetic and Logic  NEG, NEGA, NEGB Negate memory or accumulator  SBA Subtract B from A  SBCA, SBCB Subtract with carry  SUBA, SUBB, SUBD Subtract memory from accumulator

51. 330_0251 Arithmetic and Logic  COM, COMA, COMB Complement memory or accumulator  ANDA, ANDB AND memory with accumulator  ORAA, ORAB OR memory with accumulator  EORA, EORB Exclusive OR memory with accumulator

52. 330_0252 Load and Store  LDAA, LDAB, LDD, LDX Load accumulator or index register from memory  STAA, STAB, STD, STX Store accumulator or index register into memory  TAB, TBA Transfer (copy) A to B or B to A  TPA Transfer condition codes to A

53. 330_0253 Testing and Branching  TST, TSTA, TSTB Test memory or accumulator  CLR, CLRA, CLRB Clear memory or accumulator  CLC, CLV Clear the carry or overflow  SEC, SEV Set the carry or overflow  BRA Branch always Relative addressing  JMP Jump (always) Extended, indexed addressing  NOP No operation

54. 330_0254 Testing and Branching  BMI Branch on minus  BPL Branch on plus  BEQ Branch on equal to zero  BNE Branch on not equal to zero  BCC Branch on carry clear  BCS Branch on carry set  BVC Branch on overflow clear  BVS Branch on overflow set

55. 330_0255 Comparison Branching  CBA Compare B to A  CMPA, CMPB Compare accumulator to memory  CPX Compare X to memory  SBA, SUBA, SUBB Subtraction

56. 330_0256 Comparison Branching  BGT Branch if greater than  BGE Branch if greater than or equal to  BLT Branch if less than  BLE Branch if less than or equal to  BHI Branch if higher  BHS Branch if higher or same  BLO Branch if lower  BLS Branch if lower or same

57. 330_0257 Instruction Summary  Arithmetic and Logic  Load and Store Input and Output  Testing and Branching

58. 330_0258 Machine Language Programming  Minimum Requirements of a Good Program  Example Copy a Table  Basic Program Loop Pointer Counter

59. 330_0259 Minimum Requirements of a Good Program  The program must: do the same thing every time not modify itself work correctly for all reasonable data values  The program should: separate instructions and data in memory adapt easily to different sets of data start at the first instruction and stop at the last

60. 330_0260 Copy a Table Example BeforeAfter  C11011C11011 C11122C11122 C11233C11233 C11344C11344  C13037C13011 C13102C13122 C1327AC13233 C133C1C13344 

61. 330_0261 Brainstorming  Possible Approaches Copy-a-table Instruction Copy a Memory Byte Load and Store A Loop

62. 330_0262 Basic Program Loop  Pointer Points to the table entry to be copied Index Register X  Counter Counts entries to be copied Memory Register  Counting Method Initialize to number of entries Decrement to zero

63. 330_0263 Pointer and Counter  04Counter  X C11011  Pointer C11122 C11233A C11344  C13037 C13102 C1327A C133C1 

64. 330_0264 Basic Program  Initialize Pointer  Initialize Counter  Break out of Loop  Copy One Entry  Advance Pointer  Decrement Counter  Loop  Stop

65. 330_0265 Copy Table Program AddressContentsInstructionDescription  0030C1Address of first table 003110 003204Table length 0033xxWorking counter  C010DELDX DIRInitialize pointer to C01130first table C01296LDAA DIRGet initial counter C01332value C01497STAA DIRStore initial counter C01533into working counter

66. 330_0266 Copy Table Program AddressContentsInstructionDescription C01627BEQ RELBranch to STOP (+10) if C0170Acounter equals zero C018A6LDAA IND,XGet next entry from C01900first table C01AA7STAA IND,XPut entry into C01B20second table C01C08INXAdvance pointer C01D7ADEC EXTDecrement working counter C01E00 C01F33 C02020BRA RELLoop (-12) to BEQ C021F4 C0223FSTOPStop the program

67. 330_0267 Limitations and Problems  Location of Tables  Size of Tables  Branch Dependency  Mixing of program and data

68. 330_0268 Improved Copy Table Program AddressContentsInstructionDescription  0020C2Address of first table 002120 002220Spacing between tables 002304Table length 0024xxWorking counter 0025xxSave pointer 0026xx  C100DELDX DIRGet address of C10120first table C102DFSTX DIRStore in save pointer C10325location

69. 330_0269 Improved Copy Table Program AddressContentsInstructionDescription C10496LDAA DIRGet initial counter C10523value C10697STAA DIRStore initial counter C10724into working counter C108D6LDAB DIRGet table spacing C10922 C10A7DTST EXTTest working counter C10B00 C10C24 C10D27BEQ RELBranch to STOP (+17) if C10E11counter equals zero C10FDELDX DIRRestore pointer to C11025first table

70. 330_0270 Improved Copy Table Program AddressContentsInstructionDescription C111A6LDAA IND,XGet next entry from C11200first table C1133AABX INHAdjust ptr to second table C114A7STAA IND,XPut entry into C11500second table C1167ADEC EXTDecrement working counter C11700 C11824 C119DELDX DIRGet pointer value C11A25 C11B08INXAdvance pointer C11CDFSTX DIRStore pointer C11D25

71. 330_0271 Improved Copy Table Program AddressContentsInstructionDescription C11E20BRA RELLoop (-22) to TST C11FEA C12020BRA RELLoop to Here C121FE(Stop) 

72. 330_0272 Summary  Minimum Requirements of a Good Program  Basic Program Loop Pointer Counter  Example Copy a Table Improved Copy Table Program