1 of 14 1 Analysis of Mixed Time-/Event-Triggered Distributed Embedded Systems Paul Pop, Traian Pop, Petru Eles, Zebo Peng Embedded Systems Laboratory (ESLAB) Linköping University, Sweden

2 of 14 2 Application Model  Application  Set of process graphs  Each process graph G has a period T G and a deadline D G  Local release times for processes and local deadlines are supported  Each process P i has a WCET C i  Each message m has a size s m  Loops  Functional loops are unrolled  Control loops are modeled as a process graph (or process)

3 of 14 3 Platform Example FlexRay TTP TTPTime Triggered Protocol CANController Area Network FlexRay Distributed application SCS FPS SCS FPS EDF SCSStatic Cyclic Scheduling FPSFixed-Priority Preemptive EDFEarliest Deadline First

4 of 14 4 State-of-the-Art Response Time Analysis  Handles fixed-priority scheduling and earliest deadline first  Periodic (including periodic with jitter)  Aperiodic (distribution function)  Sporadic (aperiodic events with d min )  Burst (aperiodic with upper bound on the events in a given interval)  Assumptions  Arbitrary deadlines (D > T), offsets (O > T) and jitter (J > T)  Arbitrary release times: offsets are not synchronized  Dynamic offsets (given as an interval)  Example state-of-the-art analysis  González Harbour’s group at the University of Cantabria, Spain  MAST tool:

5 of 14 5 Our Extensions to the State-of-the-Art  Impact of TT on ET  On the same processor  On different processors... ET can only run in the slacks of TT Reduced ET pessimism through offsets  Communication delays on the bus  Event-driven messages on TTP  Universal communication model: TTP+CAN  FlexRay  Delays due to queuing at gateways

6 of 14 6 Mixed TT/ET Analysis Tool  Analysis theory  Exact analysis: sufficient & necessary  Implementation  Scalability  Pseudo-polynomial  Holistic, but fixed-point per resource  C implementation  GUI using the Generic Modeling Environment Sufficient but not necessary Intractable

7 of 14 7 Case Study  Case Study  4 process graphs, T = 460  28 processes on 5 processors  26 messages  Scheduling: SCS, FPS, EDF  UCM bus (TT+ET phases)  Results  Worst-case end-to-end delay  Process graph 1: 133; 2: 174; 3: 51; 4: 355  Comparisons with other approaches  Results can be produced for different platform configurations