A Depth-First-Search Controlled Gridless Incremental Routing Algorithm for VLSI Circuits Hasan Arslan and Shantanu Dutt Electrical & Computer Eng. University of Illinois at Chicago ICCD 2004

Outline Introduction Importance of Incremental Routing Previous work Our Goals A DFS-Based Incr. Routing Alg. Non-Uniform Grids DSR (Depth first search controlled Segment bump and Refit) Algorithm Experimental Results Conclusion

Introduction In current VLSI Chip The size gets smaller High clock frequency Interconnections on chip very important Technical Problems Wire-congestion and routability Crosstalk / noise Power consumption Terminal distribution

Incremental Routing After a chip layout is completed Time/noise violation One or more optimization metrics Technology constraints Make changes to the circuit/system Engineering Change Order (ECO) process Time to meet market requirements Enormous resources and time already spent. Need a time-efficient & effective incremental routing algorithm

Incremental Routing Problem Set of existing routed nets R Set of new nets S (due to timing violation, noise…) Quality metrics for an Incr. Routing Near-optimal incr. solutions in a short amount of time Preserve previous routing results as much as possible Complete the required incremental routing in the available channel area if such a solution exists Incremental Routing (Cont.)

Prior work on Incremental Routing 1) Emmert and Bhatia, “Incremental Routing in FPGA”, IEEE Int. ASIC Conference, ) Cong and Sarrafzadeh, “Incremental Physical Design”, ISPD ) Dutt, Shanmugavel and Trimberger, “Efficient Incremental Rerouting for Fault Reconfiguration in FPGAs”, ICCAD ) Dutt, Verma and Arslan “A Search-Based Bump and Refit Approach to Incremental Routing for ECO Applications in FPGAs”, TODAES ) Xiang, Chao, Wong “An ECO Algorithm for Eliminating Crossalk Violations”, ISPD 2004

Emmert-Bhatia (ASIC’98) Nets connected to faulty PLB, deleted and rerouted A graph is built, from source pin to target pin Standard single-net routing mode (global then detailed) Do not perturb or move existing nets Single Net Routing : Route new nets without removing any existing nets. Rip & Reroute : If some nets cannot be routed, rip-up the existing nets which occupy the resources of new nets. Reroute the ripped up nets. Cong-Sarrafzadeh (ISPD’00)

Dutt, Shanmugavel and Trimberger (ICCAD’99) Used incremental rerouting for dynamic fault reconfiguration in FPGAs Does not rip-up and reroute Shift them (or their subnets) to other track positions --- Bump-&-Refit (B&R) No change in topology, length of existing nets Optimal: Finds a detailed route if exists Dutt, Verma and Arslan (TODAES’02) Extended basic B&R significantly for: –full incremental routing (global + detailed) –complex switchboxes –much better results than Std and R&R (routing succ within avail res, HP of failed nets, speed under certain conditions)

Our Goals Incremental routing for VLSI (ASIC) circuits Gridless framework for non-uniform width & spacing req. and memory & time efficiency Address the quality metrics of incr. routing –Near-optimal incr. solutions (min. WL and vias) in a short amt. of time –Preserve previous routing results as much as possible –Complete the required incremental routing in the available channel area if such a solution exists = min. # of metal layers = max. routing success in given layers Approach: –Allow bumping of existing nets for near-optimal solns to new nets –However, to obtain an overall good solution  control the amount of perturbation of existing nets or their routing failures by retracting their bumpings using an overall DFS control

n1n1 n 2 n 1 n 2 Adjacent-via DFS-Based Incr. Routing Alg. ( Incr. Routing Concepts ) R-BBox

If there is an edge between two nets in OG, they might bump each other during shifting one of them. DFS-Based Incr. Routing Alg. ( Incr. Routing Concepts ) For net n i in OG higher degree (more adj. net in OG)  might bump more nets, passing through in dense area Check only adj. nets/blocks in OG to create non-uniform grid for n i CG ofn n 1 n 2 n 1. h 1 n 2. h 1 n v 1 n 1. v 1 ob 1 n 1. v 1 n h 1 n 2. v 1 n h 1 ob 1 1 CG ofn 2 possible overlapping

All paths in Cp tested? DFS-Based Incr. Routing Alg. Generate grid line in R-BB Soln? Route-with-Bumping(n i ) For each bumped net n k Do-DFS-Routing(n k ) Soln? Retract curr. bumping-causing routing path return(succ.) Cp=Get-Candidate-Paths return(succ.) Do-DFS-Routing(n i ) Route-with-Bumping(n i ) Route-without-Bumping(n i ) Soln? return(fail) NO YES return(fail)

Non-Uniform Grid Extraction Variable width/spacing rule To route new net Create obstruction zone around existing nets Find zero width path for new net Width / space req. of new net

Non-Uniform Grid Extr. & Routing s BGLs (Boundary Grid Lines) OGLs (Occupied Grid Lines) VGLs (Vacant Grid Lines) t Use VGLs to get solution without bumping. Use VGLs and OGLs to do B&R type routing (OGLs has higher cost than VGLs).

DFS-Based Incr. Routing Alg. Generate grid line in R-BB Soln? Route-with-Bumping(n i ) For each bumped net n k Do-DFS-Routing(n k ) Soln? Retract curr. bumping-causing Routing path return(succ.) Cp=Get-Candidate-Paths All paths in Cp tested? return(succ.) Do-DFS-Routing(n i ) Route-with-Bumping(n i ) Route-without-Bumping(n i ) Soln? return(fail) NO YES return(fail) YES NO Get-Next-Path(CP)

Finding Solution without Bumping – Use the 4- via Algorithm (Carothers,Lee,T-CS,1999) n 1 n 2 n 3 n 2 1-via routing Adj-via Adj-via n 1 n 1 2-via routing Adj-via Adj-via n 1 n 1 3-via routing Adj-via Adj-via n 1 n 1 cv 4-via routing Adj-via Adj-via n j Bumped seg. If 1-via path cannot be found due to obstaclesIf 2-via path cannot be found due to obstaclesIf 3-via path cannot be found due to obstacles

DFS-Based Incr. Routing Alg. For each bumped net n k Do-DFS-Routing(n k ) Soln? Retract curr. bumping-causing Routing path All paths of Cp tested? return(succ.) Do-DFS-Routing(n i ) Route-with-Bumping(n i ) NO YES return(fail) YES NO Get-Next-Path(Cp) Generate grid line in R-BB solution Route-with-Bumping(n i ) return(succ.) Route-without-Bumping(n i ) Soln? return(fail) NO YES Cp=Get-Candidate-Paths

Selecting Paths to Route Bumped Seg. Adj-via n 1 n 1 Random m paths Adj-via n 1 n 1 Equal distance m paths Adj-via n 1 n 1 The first m paths The randomized initial path set selection gave the best solutions in terms of both quality and runtime.

DFS-Based Incr. Routing Alg. For each bumped net n k Do-DFS-Routing(n k ) solution Retract previous bumping-causing routing Have all path of CP tested return(succ.) Do-DFS-Routing(n i ) Route-with-Bumping(n i ) NO YES return(failed) YES NO Get-Next-Path(CP) Generate grid line in R-BB Soln? Route-with-Bumping(n i ) return(succ.) Route-without-Bumping(n i ) Soln? return(failed) NO YES Cp=Get-Candidate-Paths

DFS-Controlled Routing with Bump & Refit n1n1 njnj n2n2 n3n3 n 1..b-seg n 2..h 2 n 3..h 1 n 3..v 1 njnj n 1.b-seg njnj n 2..h 1 P i = i-via path is explored n 1..b-seg n 2.pin or obs P1P1

DFS-Controlled Routing with Bump & Refit n1n1 njnj n2n2 n3n3 n 2..h 2 n 3..h 1 n 3..v 1 njnj n 1.b-seg n 2.pin or obs P1P1 njnj n 2..h 1 P i = i-via path is explored n 2.h 2 P2P2 n 3.v 1 P1P1 n 1..b-seg n 2..h 2

DFS-Controlled Routing with Bump & Refit n1n1 njnj n2n2 n3n3 n 3..v 1 njnj n 1.b-seg n 2.pin or obs P1P1 njnj n 2..h 1 P i = i-via path is explored n 2.h 2 P2P2 n 3.v 1 P1P1 n 1..b-seg n 2..h 2 P1P1 obs P1P1 anc obs or anc.n 1 or anc.n j P 2 -P 4 n 3..h 1 n 3..v 1 n 2..h 2

DFS-Controlled Routing with Bump & Refit n1n1 njnj n2n2 n3n3 n 3..v 1 njnj n 1.b-seg n 2.pin or obs P1P1 njnj n 2..h 1 P i = i-via path is explored n 2.h 2 P2P2 n 3.v 1 P1P1 n 1..b-seg P1P1 obs P1P1 anc obs or anc.n 1 or anc.n j P 2 -P 4 n 3..h 1 n 3..v 1 n 3.h 1 P 2 -P 3 n 2..h 2 obs P1P1 obs or anc.n 1 or anc.n j P 2 -P 4

DFS-Controlled Routing with Bump & Refit n1n1 njnj n2n2 n3n3 n 3..v 1 njnj n 1.b-seg n 2.pin or obs P1P1 njnj n 2..h 1 P i = i-via path is explored n 2.h 2 P2P2 n 3.v 1 P1P1 n 1..b-seg P1P1 obs P1P1 anc obs or anc.n 1 or anc.n j P 2 -P 4 n 3.h 1 P 2 -P 3 n 2..h 2 obs P1P1 obs or anc.n 1 or anc.n j P 2 -P 4 n 3..h 1 n 3..v 1 n 2..h 2

DFS-Controlled Routing with Bump & Refit n1n1 njnj n2n2 n3n3 n 3..v 1 njnj n 1.b-seg n 2.pin or obs P1P1 njnj P i = i-via path is explored n 2.h 2 P2P2 n 3.v 1 P1P1 n 1..b-seg P1P1 obs P1P1 anc obs or anc.n 1 or anc.n j P 2 -P 4 n 3.h 1 P 2 -P 3 obs P1P1 obs or anc.n 1 or anc.n j P 2 -P 4 n 3..h 1 n 3..v 1 n 2..h 2 n 2.h 1 P2P2 n 2..h 1 obs P1P1 n 1..b-seg

DFS-Controlled Routing with Bump & Refit n1n1 njnj n2n2 n3n3 n 3..v 1 njnj n 1.b-seg n 2.pin or obs P1P1 njnj P i = i-via path is explored n 2.h 2 P2P2 n 3.v 1 P1P1 P1P1 obs P1P1 anc obs or anc.n 1 or anc.n j P 2 -P 4 n 3.h 1 P 2 -P 3 obs P1P1 obs or anc.n 1 or an.n j P 2 -P 4 n 3..h 1 n 3..v 1 n 2..h 2 n 2.h 1 P2P2 obs P1P1 VGL P2P2

Characteristics of Benchmark Circuits –Width of net unit –Space req. btw. nets unit –Base 2x2 tile of Mcc1 benchmark is replicated with diff. cell sizes and diff. # of pins –Nets connected to pins randomly generated routed by using max 4-via routing –Experiment involved routing as many nets as possible under the constraint of 2 metal layers only  routing succ. rate = efficacy of router

Experimental Results

Experimental Results (Comparison of Failed Nets) Unrouted nets are longer and wider when Std. and R&R used DSR gets more compact layout by routing more and wider nets

Experimental Results (Comparison of Modified Nets)

Experimental Results (Global Nets)

Conclusions New Incremental Routing Algorithm DSR –gridless routing –variable width/space Produces significant impr. over Std. R&R –Via incr. of modified nets (3 (5) times less than R&R, 10% and 20%, respectively) –Higher routing success rate (Std.=10.8 (8.5) R&R= 4.6 (2.4) times worse) –Wire length (HPBB) of failed nets: Std. = 36.7 (6.59) R&R = 5.1 (2.15) times worse) –Degree of modification (~20% less modification than R&R) Future Work –Tile-based approach to avoid congestion –Timing-driven DSR algorithm

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