Timing sign-off with PrimeTime Speaker: Bob Tsai Advisor: Jie-Hong Roland Jiang

Outline Introduction Flow On Chip Variation (OCV) Manual/automated netlist editing Signal integrity and crosstalk

Introduction PrimeTime VX, PrimeTime SI Sign-off A collective name to a series of verification steps Standard Parasitic Exchange Format Represent parasitic data of wires in a chip in ASCII format Used for delay calculation and ensuring the signal integrity Firstly, I am going to introduce primetime. Primetime is an timing analysis tool developed by synopsys, and there are two sub-suite of primetime – primetime VX and primetime SI respectively. Primetime VX is the one integrated with variation-aware static timing analysis while primetime SI is integrated with crosstalk delay and noise analysis. And then I am going to introduce two terminologies. The first one is “sign-off”. Sign-off is a collective name to a series of verification steps. Thus, timing sign-off is a series of verification steps about timing issues of the chip. The second one is Standard Parasitic Exchange Format, SPEF in short. It is an IEEE standard, representing parasitic data of wires in a chip in ASCII format, and it is commonly used for delay calculation and ensuring signal integrity.

Flow Setup Design Update RTL Check setup Update CHIP level STA SDC Create CHIP constraints Check setup Validate Prelayout Constraints Update SDC CHIP level STA fail Timing error? Validate Constraints Hand-off pass Update SDC This is the typical flow of timing sign-off. After setting up the constraints of the chip, we perform the static timing analysis. If the chip fails STA, we first update the Synopsys Design Constraints file and perform STA again. If the chip still cannot pass, then the RTL will be updated. The STA is succeeded by the P&R, and similarly SDC will be updated if there is any timing error. However, the chip could be taped out with none of the timing error. And notice that the main difference of these two timing checks is that the former one use wire load model to estimate the loads while the later one uses parasitic file extracted by STARRC for more detailed information. P&R Validate Postlayout Constraints fail Timing error? pass Tape-out

On Chip Variation Models the small difference in operating parameters across the chip Setup check: max delay for data path and min delay for clock path Hold check: min delay for data path and max delay for clock path OCV, on chip variation, is the variation due to the advanced process. It models the small difference in operating parameters across the chip For example, when we want to check for both setup time and hold time, we take not only one delay but maximum and minimum delay of a path into account. For the setup time checking, the delay of data path should be the maximum while the counterpart of clock path should be the minimum. Vice versa for the hold time checking for the best case.

Setup Time Checking Clock path 1 + data path max – clock path 2 + setup ≤ clock period max = 3.04/3.8 D Q logic D Q 0.48/0.6 min = 1.6/2.0 CT3 0.64/0.8 0.52/0.65 setup = 0.2 CLK CT1 CT2 Let’s have an example for the setup time checking. The numbers separated by the slash are the two peak delays of the path. In this example, the maximum delay of the data path of the right D flip-flop is 3.8 and the minimum delay of the left clock path is 1.4 while the maximum delay of the right clock path is 1.16 Then we can get the minimum clock period by adding the maximum data path, the setup time, and the difference between two clock path delays in order to meet the setup time. Clock path 1 = 0.8+0.6 =1.4 Data path max = 3.8 Clock path 2 = 0.64+0.52=1.16 Setup = 0.2 => The clock period must be at least 1.4+3.8-1.16+0.2=4.24

Hold Time Checking Clock path 1 + data path min – clock path 2 - hold ≥ 0 max = 3.04/3.8 D Q logic D Q 0.48/0.6 min = 1.6/2.0 CT3 0.64/0.8 0.52/0.65 hold = 0.1 CLK CT1 CT2 As for the hold time checking, the minimum data path delay is 1.6 And the minimum delay of the left clock path is 1.12 while the maximum delay of the right clock path is 1.45 Assume the hold time is 0.1 Then we can find out that there’s no hold time violation Clock path 1 = 0.64+0.48 =1.12 Data path min = 1.6 Clock path 2 = 0.8+0.65=1.45 Hold = 0.1 => No hold violation exists because 1.12+1.6-1.45-0.1=1.17 ≥ 0

Functions for check and analysis Commands Main functions set_wire_load_model (before P&R) read_sdf (after P&R) read_parasitics check_timing Checks for constraint problem such as undefined clocking, input data arrival times, and output data required times. (must-do) report_design Lists the attributes of the design, including the chosen operating conditions, wire load information, and design rules. report_clock Generates a report on the clocks defined for the design, showing for each clock the name, period, rise and fall times, and timing characteristics such as latency and uncertainty. Then I’m going to introduce some functions. Before place and route, PrimeTime estimates the loads by using the wire load model provided in the technology library. But after place and route, more detailed net delay information are needed for a layout-accurate timing analysis. Thus, standard delay file or parasitic file is used. Check timing is a must-do command because it checks whether there is any timing data undefined. Report design can list the attributes of the design and report clock can list the timing characteristics of the clocks defined for the design.

Manual Netlist Editing size_cell insert_buffer | remove_buffer swap_cell Use write_change to output the changes After checking the design, there are some commands that could be used to modify the netlist manually. The first one is size cell. Size cell is used to resize the cell, and most of the time it upsizes the cell instead of downsizing. Besides, many kinds of buffer could be inserted, or removed. The last one is swap cell. Just as its name indicates, this command is used to swap cells. After manually editing the netlist, we can use write change to output the changes we did.

Automated Netlist Editing The design should be fully placed and routed, including clock trees, but without corefiller fix_eco_timing –type {setup | hold} fix_drc_timing –type {max_transition | max_capacitance | max_fanout} –method {size_cell | insert_buffer} In addition to manually editing, automated editing is supported as well. But notice that there are some constraints – the design should be fully placed and routed, and without corefiller. The reason why there should not be any corefiller is because once the corefiller has been added, there is no room for automated editing to add some buffers. If we want to fix the setup time or hold time, we can use fix eco timing to fix the one specified. On the other hand, if we want to fix or reduce the maximum transition, capacitance, or fanout, we can use fix drc timing. Furthermore, we can choose the method we want, by sizing the cell or by inserting buffers. /////Use fix_eco_timing to by resizing the cellls and we can determine which among setup and hold time to be fixed. pt_shell> fix_drc_timing –type max_transition –method {size_cell} -verbose pt_shell> fix_drc_timing –type max_transition –method {insert_buffer} -buffer_list {BUFX1 BUFX2 BUFX3} -verbose

Signal Integrity and Crosstalk The ability of an electrical signal to carry information reliably and resist the effects of high- frequency electromagnetic interference from nearby signals Crosstalk The undesirable electrical interaction between two or more physically adjacent net due to capacitive cross-coupling Then I’m going to introduce the signal integrity and crosstalk. Signal integrity is the ability of signal to carry information reliably, resisting the effects of the electromagnetic interference from the nearby high-frequency signals. And the crosstalk is the interaction between two or more nets due to the capacitive cross-coupling. As the picture shows, net B is the victim while net A and C are aggressors. And we can see that both A and C can interfere the signal on B individually. In consequence, the signal on B is the superposition of both impacts from A and C.

Noise analysis flow ∙ set si_enable_analysis TRUE Enable crosstalk analysis ∙ set si_enable_analysis TRUE Read coupled parasitic data ∙ read_parasitics -format spef -keep_capacitive_coupling [spef_filename] Do coupled delay analysis ∙ update_timing This is the typical flow of noise analysis. Firstly, we should enable primetime SI, which is an add-on feature that is capable of analyzing the crosstalk. Second, we should read in the SPEF file to get the parasitic data. Notice that the argument keep capacitive coupling is necessary to maintain the cross-coupling status of the capacitors that have been read into PT. After having the parasitic data, we can use update timing to detect timing violations resulting from the effects of crosstalk. Then we can use update noise to detect functional errors resulting from the crosstalk. At last, the noise can be reported by report noise. Noise analysis ∙ update_noise Generate noise report ∙ report_noise

Thanks for your attention

Clock Setup logic set_false_path set_clock_group CLK1 CLK3 1 1 CLK2 D Q D Q CLK1 CLK3 CLK2 1 CLK4 1 SEL set_false_path set_clock_group set_false_path –from CLK1 –to CLK2 set_false_path –from CLK2 –to CLK1 set_false_path –from CLK3 –to CLK4 set_false_path –from CLK4 –to CLK3 set_false_path –from CLK1 –to CLK4 set_false_path –from CLK4 –to CLK1 set_false_path –from CLK2 –to CLK3 set_false_path –from CLK3 –to CLK2 set_clock_groups \ -logically_exclusive –name E1 \ -group {CLK1 CLK3} -group {CLK2 CLK4} set_active_clock [all_clocks] We can use “set_false_path” to specify which path will never be gone through. In this circuit we can see that there shouldn’t be a path from CLK1 to CLK2 and same as those 7 paths below. Besides, we can group up clocks, indicating their mutual-exclusive.