A Novel Cell Placement Algorithm For Flexible TFT Circuit With Mechanical Strain And Temperature Consideration Jiun-Li Lin, Po-Hsun Wu, and Tsung-Yi Ho.

Slides:



Advertisements
Similar presentations
THERMAL-AWARE BUS-DRIVEN FLOORPLANNING PO-HSUN WU & TSUNG-YI HO Department of Computer Science and Information Engineering, National Cheng Kung University.
Advertisements

Algorithm for Fast Statistical Timing Analysis Jakob Salzmann, Frank Sill, Dirk Timmermann SOC 2007, Nov ‘07, Tampere, Finland Institute of Applied Microelectronics.
A Graph-Partitioning-Based Approach for Multi-Layer Constrained Via Minimization Yih-Chih Chou and Youn-Long Lin Department of Computer Science, Tsing.
Optimization of Placement Solutions for Routability Wen-Hao Liu, Cheng-Kok Koh, and Yih-Lang Li DAC’13.
Topology-Aware Buffer Insertion and GPU-Based Massively Parallel Rerouting for ECO Timing Optimization Yen-Hung Lin, Yun-Jian Lo, Hian-Syun Tong, Wen-Hao.
Xing Wei, Wai-Chung Tang, Yu-Liang Wu Department of Computer Science and Engineering The Chinese University of HongKong
Wen-Hao Liu1, Yih-Lang Li, and Cheng-Kok Koh Department of Computer Science, National Chiao-Tung University School of Electrical and Computer Engineering,
3D-STAF: Scalable Temperature and Leakage Aware Floorplanning for Three-Dimensional Integrated Circuits Pingqiang Zhou, Yuchun Ma, Zhouyuan Li, Robert.
Meng-Kai Hsu, Sheng Chou, Tzu-Hen Lin, and Yao-Wen Chang Electronics Engineering, National Taiwan University Routability Driven Analytical Placement for.
A Size Scaling Approach for Mixed-size Placement Kalliopi Tsota, Cheng-Kok Koh, Venkataramanan Balakrishnan School of Electrical and Computer Engineering.
Shuai Li and Cheng-Kok Koh School of Electrical and Computer Engineering, Purdue University West Lafayette, IN, Mixed Integer Programming Models.
National Tsing Hua University Po-Yang Hsu,Hsien-Te Chen,
Paul Falkenstern and Yuan Xie Yao-Wen Chang Yu Wang Three-Dimensional Integrated Circuits (3D IC) Floorplan and Power/Ground Network Co-synthesis ASPDAC’10.
Coupling-Aware Length-Ratio- Matching Routing for Capacitor Arrays in Analog Integrated Circuits Kuan-Hsien Ho, Hung-Chih Ou, Yao-Wen Chang and Hui-Fang.
Row-Based Area-Array I/O Design Planning in Concurrent Chip-Package Design Flow R. Lee and H. Chen Department of EE NCTU, Taiwan ASPDAC 2011.
An ILP-based Automatic Bus Planner for Dense PCBs P. C. Wu, Q. Ma and M. D. F. Wong Department of Electrical and Computer Engineering, University of Illinois.
1 Thermal Via Placement in 3D ICs Brent Goplen, Sachin Sapatnekar Department of Electrical and Computer Engineering University of Minnesota.
Po-Hsun Wu*, Mark Po-Hung Lin**, Xin Li***, and Tsung-Yi Ho**** *Dept. of CSIE, National Cheng Kung University, Tainan, Taiwan ** Dept. of EE, National.
VLSI/CAD Laboratory Department of Computer Science National Tsing Hua University TH EDA Estimation of Maximum Instantaneous Current for Sequential Circuits.
Boosting: Min-Cut Placement with Improved Signal Delay Andrew B. KahngSherief Reda CSE & ECE Departments University of CA, San Diego La Jolla, CA
38 th Design Automation Conference, Las Vegas, June 19, 2001 Creating and Exploiting Flexibility in Steiner Trees Elaheh Bozorgzadeh, Ryan Kastner, Majid.
1 DAOmap: A Depth-optimal Area Optimization Mapping Algorithm for FPGA Designs Deming Chen, Jacon Cong ICCAD 2004 Presented by: Wei Chen.
A Timing-Driven Soft-Macro Resynthesis Method in Interaction with Chip Floorplanning Hsiao-Pin Su 1 2 Allen C.-H. Wu 1 Youn-Long Lin 1 1 Department of.
Merging Synthesis With Layout For Soc Design -- Research Status Jinian Bian and Hongxi Xue Dept. Of Computer Science and Technology, Tsinghua University,
Detailed Placement for Leakage Reduction Using Systematic Through-Pitch Variation Andrew B. Kahng †‡ Swamy Muddu ‡ Puneet Sharma ‡ CSE † and ECE ‡ Departments,
Layout-based Logic Decomposition for Timing Optimization Yun-Yin Lien* Youn-Long Lin Department of Computer Science, National Tsing Hua University, Hsin-Chu,
Triple Patterning Aware Detailed Placement With Constrained Pattern Assignment Haitong Tian, Yuelin Du, Hongbo Zhang, Zigang Xiao, Martin D.F. Wong.
Memory-Efficient Regular Expression Search Using State Merging Department of Computer Science and Information Engineering National Cheng Kung University,
1 Reconfigurable ECO Cells for Timing Closure and IR Drop Minimization TingTing Hwang Tsing Hua University, Hsin-Chu.
Page 1 Department of Electrical Engineering National Chung Cheng University, Chiayi, Taiwan Power Optimization for Clock Network with Clock Gate Cloning.
A Topology-based ECO Routing Methodology for Mask Cost Minimization Po-Hsun Wu, Shang-Ya Bai, and Tsung-Yi Ho Department of Computer Science and Information.
Authors: Jia-Wei Fang,Chin-Hsiung Hsu,and Yao-Wen Chang DAC 2007 speaker: sheng yi An Integer Linear Programming Based Routing Algorithm for Flip-Chip.
Dr.M.V.Rama Rao Department of Civil Engineering,
NCKU CSIE EDALAB Department of Computer Science and Information Engineering National Cheng Kung University Tainan, Taiwan Tsung-Wei.
Global Routing.
Pattern Selection based co-design of Floorplan and Power/Ground Network with Wiring Resource Optimization L. Li, Y. Ma, N. Xu, Y. Wang and X. Hong WuHan.
TSV-Aware Analytical Placement for 3D IC Designs Meng-Kai Hsu, Yao-Wen Chang, and Valerity Balabanov GIEE and EE department of NTU DAC 2011.
Wen-Hao Liu 1, Yih-Lang Li 1, and Kai-Yuan Chao 2 1 Department of Computer Science, National Chiao-Tung University, Hsin-Chu, Taiwan 2 Intel Architecture.
New Modeling Techniques for the Global Routing Problem Anthony Vannelli Department of Electrical and Computer Engineering University of Waterloo Waterloo,
A NEW ECO TECHNOLOGY FOR FUNCTIONAL CHANGES AND REMOVING TIMING VIOLATIONS Jui-Hung Hung, Yao-Kai Yeh,Yung-Sheng Tseng and Tsai-Ming Hsieh Dept. of Information.
Improved Cut Sequences for Partitioning Based Placement Mehmet Can YILDIZ and Patrick H. Madden State University of New York at BinghamtonComputer Science.
Thermal-aware Steiner Routing for 3D Stacked ICs M. Pathak and S.K. Lim Georgia Institute of Technology ICCAD 07.
Bus-Pin-Aware Bus-Driven Floorplanning B. Wu and T. Ho Department of Computer Science and Information Engineering NCKU GLSVLSI 2010.
Massachusetts Institute of Technology 1 L14 – Physical Design Spring 2007 Ajay Joshi.
Ho-Lin Chang, Hsiang-Cheng Lai, Tsu-Yun Hsueh, Wei-Kai Cheng, Mely Chen Chi Department of Information and Computer Engineering, CYCU A 3D IC Designs Partitioning.
Keh-moh Lin ∗, Paijay Tsai Department of Mechanical Engineering, Southern Taiwan University of Technology, No. 1, Nantai St., Yung-Kang City, Tainan 710,
ECO Timing Optimization Using Spare Cells Yen-Pin Chen, Jia-Wei Fang, and Yao-Wen Chang ICCAD2007, Pages ICCAD2007, Pages
Tao Lin Chris Chu TPL-Aware Displacement- driven Detailed Placement Refinement with Coloring Constraints ISPD ‘15.
Pattern Sensitive Placement For Manufacturability Shiyan Hu, Jiang Hu Department of Electrical and Computer Engineering Texas A&M University College Station,
Pattern Sensitive Placement For Manufacturability Shiyan Hu, Jiang Hu Department of Electrical and Computer Engineering Texas A&M University College Station,
A SAT-Based Routing Algorithm for Cross-Referencing Biochips Ping-Hung Yuh 1, Cliff Chiung-Yu Lin 2, Tsung- Wei Huang 3, Tsung-Yi Ho 3, Chia-Lin Yang 4,
Clock-Tree Aware Placement Based on Dynamic Clock-Tree Building Yanfeng Wang, Qiang Zhou, Xianlong Hong, and Yici Cai Department of Computer Science and.
Po-Wei Lee, Chung-Wei Lin, Yao-Wen Chang, Chin-Fang Shen, Wei-Chih Tseng NTU &Synopsys An Efficient Pre-assignment Routing Algorithm for Flip-Chip Designs.
Hsing-Chih Chang Chien Hung-Chih Ou Tung-Chieh Chen Ta-Yu Kuan Yao-Wen Chang Double Patterning Lithography-Aware Analog Placement.
1 CS612 Algorithms for Electronic Design Automation CS 612 – Lecture 1 Course Overview Mustafa Ozdal Computer Engineering Department, Bilkent University.
Simultaneous Analog Placement and Routing with Current Flow and Current Density Considerations H.C. Ou, H.C.C. Chien and Y.W. Chang Electronics Engineering,
ILP-Based Inter-Die Routing for 3D ICs Chia-Jen Chang, Pao-Jen Huang, Tai-Chen Chen, and Chien-Nan Jimmy Liu Department of Electrical Engineering, National.
HEAT TRANSFER FINITE ELEMENT FORMULATION
Yu-Wei Wu Yi-Yu Shi Sudip Roy Tsung-Yi Ho3
Memory-Efficient Regular Expression Search Using State Merging Author: Michela Becchi, Srihari Cadambi Publisher: INFOCOM th IEEE International.
LEMAR: A Novel Length Matching Routing Algorithm for Analog and Mixed Signal Circuits H. Yao, Y. Cai and Q. Gao EDA Lab, Department of CS, Tsinghua University,
System in Package and Chip-Package-Board Co-Design
1ISPD'03 Process Variation Aware Clock Tree Routing Bing Lu Cadence Jiang Hu Texas A&M Univ Gary Ellis IBM Corp Haihua Su IBM Corp.
An Energy-Efficient Approach for Real-Time Tracking of Moving Objects in Multi-Level Sensor Networks Vincent S. Tseng, Eric H. C. Lu, & Kawuu W. Lin Institute.
CAD for VLSI Ramakrishna Lecture#2.
1 DESIGN AND EVALUATION OF A PIPELINED FORWARDING ENGINE Department of Computer Science and Information Engineering National Cheng Kung University, Taiwan.
The Early Days of Automatic Floorplan Design
Global topology optimization of truss structures Dmitrij Šešok Rimantas Belevičius Department of Engineering Mechanics. Vilnius Gediminas Technical University.
Hierarchical Hybrid Search Structure for High Performance Packet Classification Authors : O˜guzhan Erdem, Hoang Le, Viktor K. Prasanna Publisher : INFOCOM,
Solving maximum flows on distribution networks:
Presentation transcript:

A Novel Cell Placement Algorithm For Flexible TFT Circuit With Mechanical Strain And Temperature Consideration Jiun-Li Lin, Po-Hsun Wu, and Tsung-Yi Ho Department of Computer Science and Information Engineering, National Cheng Kung University, Tainan, Taiwan ASPDAC 2013

Outline Introduction Initial Static Timing Analysis Static Timing Analysis with Mobility Consideration Thermal-aware Non-critical Cell Distribution ILP-based Critical Cell Distribution Multilevel Global Placement Row-based Detail Placement Experimental results Conclusion

Introduction Flexible thin-film transistor (TFT) is the most popular technology used in flexible electronics due to its low fabrication temperature [11], but its performance is severely affected by the mobility variation. After extensive experiments have been performed, past researches found that TFT’s mobility will be greatly affected by the mechanical strain [4, 5, 10, 12]

Mechanical strain Mechanical strain is the mathematical expression of the shape changes resulting from mechanical stresses.

Mobility variation Mobility variation makes a great impact on the cell delay of a flexible TFT circuit which further affects the circuit performance. At worst, mobility variation may leads to timing violation and even function failure. In addition to the impact of mechanical strain, mobility is also sensitive to temperature change [13, 16].

Cell placement

Algorithm Flow

Initial Static Timing Analysis All critical cells can be further extracted by backtracking procedure in a manner similar to depth-first search (DFS).

Static Timing Analysis with Mobility Consideration The static timing analyzer for flexible TFT circuits (STAF) [6] is performed to determine the mobility influence. STAF only takes the change of mechanical strain into consideration, it is further modified by replacing equation(1) with equation(3) to consider the change of both mechanical strain and temperature.

Static Timing Analysis with Mobility Consideration

Thermal-aware Non-critical Cell Distribution Formulate this problem as a K-way graph partitioning problem to distribute all non-critical cells to different B groups while minimizing total wirelength and the chip temperature.

ILP-based Critical Cell Distribution

Exclusivity constraint: Distribution constraint:

Multilevel Global Placement

Row-based Detail Placement Initially, it will calculate how many rows can be placed in a bin and partition all cells to different rows based on cell connectivity. All cells in the same row are classified into hot cells and cool cells, and each cool cell is placed adjacent to the hot cell to reduce the temperature.

Experimental results

Conclusion The novel cell placement flow and algorithms to minimize the mobility variation caused by the change of both mechanical strain and temperature while minimizing total wirelength.