Lecturer Michael S. McCorquodale Authors Michael S. McCorquodale, Fadi H. Gebara, Keith L. Kraver, Eric D. Marsman, Robert M. Senger, and Richard B. Brown.

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Presentation transcript:

Lecturer Michael S. McCorquodale Authors Michael S. McCorquodale, Fadi H. Gebara, Keith L. Kraver, Eric D. Marsman, Robert M. Senger, and Richard B. Brown A Top-Down Microsystems Design Methodology and Associated Challenges Solid State Electronics Laboratory Center for Wireless Integrated Microsystems Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor, MI USA Design Automation and Test Europe Conference, Munich, Germany, March 2003

2 Michael S. McCorquodale University of Michigan Outline Motivation Microsystems: Anatomy Bottom-Up Design Methodology WIMS Microcontroller Design Framework Top-Down Design Methodology Gaps and Solutions Conclusions

3 Michael S. McCorquodale University of Michigan Motivation Discuss design trends and challenges in microsystems technology Leverage advances in mixed-signal SoC design automation Determine a design methodology and framework appropriate for microsystems technology Implement methodology in a microsystem design Demonstrate increased design efficiency and verification Identify gaps in tool suite and promote development of required capabilities MotivationMicrosystemsBottom-UpMicrocontrollerFrameworkTop-DownGaps & Solns.Conclusions

4 Michael S. McCorquodale University of Michigan The anatomy of a generalized wireless integrated microsystem (WIMS). Key technologies and associated development tools are shown Microsystems: Anatomy MEMSAnalogMixed-SignalDigital/VLSI Antenna Microprocessor Wireless Interface Clock Sensor/Actuator Interface Sensor Actuator Baseband Modem RFIC/RFMEMS FE Tools AHDL Custom IC Tools VHDL Synthesis Tools AHDL Custom RFIC Tools DAC ADC MS-HDL Custom IC Tools MotivationMicrosystemsBottom-UpMicrocontrollerFrameworkTop-DownGaps & Solns.Conclusions

5 Michael S. McCorquodale University of Michigan The anatomy of a generalized wireless integrated microsystem (WIMS). Key technologies and associated development tools are shown Microsystems: Anatomy MEMSAnalogMixed-SignalDigital/VLSI Antenna Microprocessor Wireless Interface Clock Sensor/Actuator Interface Sensor Actuator Baseband Modem RFIC/RFMEMS FE Tools AHDL Custom IC Tools VHDL Synthesis Tools AHDL Custom RFIC Tools DAC ADC MS-HDL Custom IC Tools MotivationMicrosystemsBottom-UpMicrocontrollerFrameworkTop-DownGaps & Solns.Conclusions

6 Michael S. McCorquodale University of Michigan The anatomy of a generalized wireless integrated microsystem (WIMS). Key technologies and associated development tools are shown Microsystems: Anatomy MEMSAnalogMixed-SignalDigital/VLSI Antenna Microprocessor Wireless Interface Clock Sensor/Actuator Interface Sensor Actuator Baseband Modem RFIC/RFMEMS FE Tools AHDL Custom IC Tools VHDL Synthesis Tools AHDL Custom RFIC Tools DAC ADC MS-HDL Custom IC Tools MotivationMicrosystemsBottom-UpMicrocontrollerFrameworkTop-DownGaps & Solns.Conclusions

7 Michael S. McCorquodale University of Michigan The anatomy of a generalized wireless integrated microsystem (WIMS). Key technologies and associated development tools are shown Microsystems: Anatomy MEMSAnalogMixed-SignalDigital/VLSI Antenna Microprocessor Wireless Interface Clock Sensor/Actuator Interface Sensor Actuator Baseband Modem RFIC/RFMEMS FE Tools AHDL Custom IC Tools VHDL Synthesis Tools AHDL Custom RFIC Tools DAC ADC MS-HDL Custom IC Tools MotivationMicrosystemsBottom-UpMicrocontrollerFrameworkTop-DownGaps & Solns.Conclusions

8 Michael S. McCorquodale University of Michigan The anatomy of a generalized wireless integrated microsystem (WIMS). Key technologies and associated development tools are shown Microsystems: Anatomy MEMSAnalogMixed-SignalDigital/VLSI Antenna Microprocessor Wireless Interface Clock Sensor/Actuator Interface Sensor Actuator Baseband Modem RFIC/RFMEMS FE Tools AHDL Custom IC Tools VHDL Synthesis Tools AHDL Custom RFIC Tools DAC ADC MS-HDL Custom IC Tools MotivationMicrosystemsBottom-UpMicrocontrollerFrameworkTop-DownGaps & Solns.Conclusions

9 Michael S. McCorquodale University of Michigan Bottom-Up Design Methodology Verification: DRC, LVS (Top Routing Only), Parasitic ExtractionandBackannotation (IC Tool) Digital SpecificationAnalog SpecificationMechanical Specification Custom Analog Design (SPICE) Custom Mechanical Design (FE) Synthesis/APR/Timing (Synthesizer) Analog Physical Design (IC Tool) Digital Library Tapeout Process Library Digital Design (HDL) Digital Domain Analog Domain Mechanical Domain Analog MacroMechanical MacroDigital Macro System Specification and Design Partition Macro Automatic Place and Route (APR and IC Tool) Verification: DRC, LVS (Top Routing Only), Parasitic ExtractionandBackannotation (IC Tool) Digital SpecificationAnalog SpecificationMechanical Specification Custom Analog Design (SPICE) Custom Mechanical Design (FE) Synthesis/APR/Timing (Synthesizer) Analog Physical Design (IC Tool) Digital Library Tapeout Process Library Digital Design (HDL) Digital Domain Analog Domain Mechanical Domain Analog MacroMechanical MacroDigital Macro System Specification and Design Partition Macro Automatic Place and Route (APR and IC Tool) MotivationMicrosystemsBottom-UpMicrocontrollerFrameworkTop-DownGaps & Solns.Conclusions

10 Michael S. McCorquodale University of Michigan Bottom-Up Design Methodology Verification: DRC, LVS (Top Routing Only), Parasitic ExtractionandBackannotation (IC Tool) Digital SpecificationAnalog SpecificationMechanical Specification Custom Analog Design (SPICE) Custom Mechanical Design (FE) Synthesis/APR/Timing (Synthesizer) Analog Physical Design (IC Tool) Digital Library Tapeout Process Library Digital Design (HDL) Digital Domain Analog Domain Mechanical Domain Analog MacroMechanical MacroDigital Macro System Specification and Design Partition Macro Automatic Place and Route (APR and IC Tool) Verification: DRC, LVS (Top Routing Only), Parasitic ExtractionandBackannotation (IC Tool) Digital SpecificationAnalog SpecificationMechanical Specification Custom Analog Design (SPICE) Custom Mechanical Design (FE) Synthesis/APR/Timing (Synthesizer) Analog Physical Design (IC Tool) Digital Library Tapeout Process Library Digital Design (HDL) Digital Domain Analog Domain Mechanical Domain Analog MacroMechanical MacroDigital Macro System Specification and Design Partition Macro Automatic Place and Route (APR and IC Tool) MotivationMicrosystemsBottom-UpMicrocontrollerFrameworkTop-DownGaps & Solns.Conclusions

11 Michael S. McCorquodale University of Michigan Bottom-Up Design Methodology Verification: DRC, LVS (Top Routing Only), Parasitic ExtractionandBackannotation (IC Tool) Digital SpecificationAnalog SpecificationMechanical Specification Custom Analog Design (SPICE) Custom Mechanical Design (FE) Synthesis/APR/Timing (Synthesizer) Analog Physical Design (IC Tool) Digital Library Tapeout Process Library Digital Design (HDL) Digital Domain Analog Domain Mechanical Domain Analog MacroMechanical MacroDigital Macro System Specification and Design Partition Macro Automatic Place and Route (APR and IC Tool) Verification: DRC, LVS (Top Routing Only), Parasitic ExtractionandBackannotation (IC Tool) Digital SpecificationAnalog SpecificationMechanical Specification Custom Analog Design (SPICE) Custom Mechanical Design (FE) Synthesis/APR/Timing (Synthesizer) Analog Physical Design (IC Tool) Digital Library Tapeout Process Library Digital Design (HDL) Digital Domain Analog Domain Mechanical Domain Analog MacroMechanical MacroDigital Macro System Specification and Design Partition Macro Automatic Place and Route (APR and IC Tool) MotivationMicrosystemsBottom-UpMicrocontrollerFrameworkTop-DownGaps & Solns.Conclusions

12 Michael S. McCorquodale University of Michigan Bottom-Up Design Methodology Verification: DRC, LVS (Top Routing Only), Parasitic ExtractionandBackannotation (IC Tool) Digital SpecificationAnalog SpecificationMechanical Specification Custom Analog Design (SPICE) Custom Mechanical Design (FE) Synthesis/APR/Timing (Synthesizer) Analog Physical Design (IC Tool) Digital Library Tapeout Process Library Digital Design (HDL) Digital Domain Analog Domain Mechanical Domain Analog MacroMechanical MacroDigital Macro System Specification and Design Partition Macro Automatic Place and Route (APR and IC Tool) Verification: DRC, LVS (Top Routing Only), Parasitic ExtractionandBackannotation (IC Tool) Digital SpecificationAnalog SpecificationMechanical Specification Custom Analog Design (SPICE) Custom Mechanical Design (FE) Synthesis/APR/Timing (Synthesizer) Analog Physical Design (IC Tool) Digital Library Tapeout Process Library Digital Design (HDL) Digital Domain Analog Domain Mechanical Domain Analog MacroMechanical MacroDigital Macro System Specification and Design Partition Macro Automatic Place and Route (APR and IC Tool) MotivationMicrosystemsBottom-UpMicrocontrollerFrameworkTop-DownGaps & Solns.Conclusions

13 Michael S. McCorquodale University of Michigan Bottom-Up Design Methodology Verification: DRC, LVS (Top Routing Only), Parasitic ExtractionandBackannotation (IC Tool) Digital SpecificationAnalog SpecificationMechanical Specification Custom Analog Design (SPICE) Custom Mechanical Design (FE) Synthesis/APR/Timing (Synthesizer) Analog Physical Design (IC Tool) Digital Library Tapeout Process Library Digital Design (HDL) Digital Domain Analog Domain Mechanical Domain Analog MacroMechanical MacroDigital Macro System Specification and Design Partition Macro Automatic Place and Route (APR and IC Tool) Verification: DRC, LVS (Top Routing Only), Parasitic ExtractionandBackannotation (IC Tool) Digital SpecificationAnalog SpecificationMechanical Specification Custom Analog Design (SPICE) Custom Mechanical Design (FE) Synthesis/APR/Timing (Synthesizer) Analog Physical Design (IC Tool) Digital Library Tapeout Process Library Digital Design (HDL) Digital Domain Analog Domain Mechanical Domain Analog MacroMechanical MacroDigital Macro System Specification and Design Partition Macro Automatic Place and Route (APR and IC Tool) MotivationMicrosystemsBottom-UpMicrocontrollerFrameworkTop-DownGaps & Solns.Conclusions

14 Michael S. McCorquodale University of Michigan Bottom-Up Design Methodology The Problems No opportunity for architectural studies Time-consuming design iteration Cross-domain verification at top level only Time-consuming system level simulation, if it is even possible MotivationMicrosystemsBottom-UpMicrocontrollerFrameworkTop-DownGaps & Solns.Conclusions

15 Michael S. McCorquodale University of Michigan WIMS Microcontroller TSMC 0.18 micron mixed-mode 16-bit 3-stage pipeline core Analog front end (AFE) MEMS-based clock generator 64KB on-chip SRAM Timer and serial interfaces 1.5 million transistors 10.24mm 2 Die micrograph of the fabricated microsystem MotivationMicrosystemsBottom-UpMicrocontrollerFrameworkTop-DownGaps & Solns.Conclusions

16 Michael S. McCorquodale University of Michigan Design Framework: Requirements System level simulation support (HDL) Cross-domain verification at any level for MEMS, analog, and digital electronics Finite element simulation Active device and HDL simulation Parasitic extraction Co-simulation of primitives and HDL Timing verification HDL synthesis Automatic place and route MotivationMicrosystemsBottom-UpMicrocontrollerFrameworkTop-DownGaps & Solns.Conclusions

17 Michael S. McCorquodale University of Michigan Design Framework: Employed Cadence AMS System modeling, primitive/HDL co-simulation, and MEMS modeling Spectre Analog device level simulation Coventorware Finite element analysis Synopsys Digital synthesis Cadence Silicon Ensemble Automatic place and route Mentor Graphics Calibre DRC, ERC, and LVS MotivationMicrosystemsBottom-UpMicrocontrollerFrameworkTop-DownGaps & Solns.Conclusions

18 Michael S. McCorquodale University of Michigan Top-Down Design Methodology Cross-Domain Verification (Verilogwith updatedVerilog-A from achieved performance and/orVerilogandVerilog-A with Primitives) Analog Model (Verilog-A) Mechanical Model (Verilog-A) Abstract System Model (Verilog-AMS:VerilogandVerilog-A) Digital Library Process Library Tapeout Digital Domain Analog Domain Mechanical Domain Cross-Domain Verification (Verilogwith updatedVerilog-A fromparasiticsand/orVerilogandVerilog-A with Primitives) Cross-Domain Verification (Verilogwith updatedVerilog-A with interconnectparasitics) Analog Macro Parasitic Extraction (IC Tool) Extraction, Timing (Timing Tool) Digital MacroMechanical Macro Parasitic Extraction (IC Tool) Custom Analog Design (SPICE) Mechanical Design (Finite Element) Macro Place and Route, Layout Verification: DRC, LVS (APR and IC Tool) Layout Parasitic Extraction (LPE) andBackannotation (IC Tool) Synthesis/APR/Timing (Synthesis Tool) Physical Design/Verif. (IC Tool) Physical Design/Verif. (IC Tool) Digital Model (Verilog) Behavioral Verification (Verilog) MotivationMicrosystemsBottom-UpMicrocontrollerFrameworkTop-DownGaps & Solns.Conclusions

19 Michael S. McCorquodale University of Michigan Top-Down Design Methodology Cross-Domain Verification (Verilogwith updatedVerilog-A from achieved performance and/orVerilogandVerilog-A with Primitives) Analog Model (Verilog-A) Mechanical Model (Verilog-A) Abstract System Model (Verilog-AMS:VerilogandVerilog-A) Digital Library Process Library Tapeout Digital Domain Analog Domain Mechanical Domain Cross-Domain Verification (Verilogwith updatedVerilog-A fromparasiticsand/orVerilogandVerilog-A with Primitives) Cross-Domain Verification (Verilogwith updatedVerilog-A with interconnectparasitics) Analog Macro Parasitic Extraction (IC Tool) Extraction, Timing (Timing Tool) Digital MacroMechanical Macro Parasitic Extraction (IC Tool) Custom Analog Design (SPICE) Mechanical Design (Finite Element) Macro Place and Route, Layout Verification: DRC, LVS (APR and IC Tool) Layout Parasitic Extraction (LPE) andBackannotation (IC Tool) Synthesis/APR/Timing (Synthesis Tool) Physical Design/Verif. (IC Tool) Physical Design/Verif. (IC Tool) Digital Model (Verilog) Behavioral Verification (Verilog) MotivationMicrosystemsBottom-UpMicrocontrollerFrameworkTop-DownGaps & Solns.Conclusions

20 Michael S. McCorquodale University of Michigan Top-Down Design Methodology Cross-Domain Verification (Verilogwith updatedVerilog-A from achieved performance and/orVerilogandVerilog-A with Primitives) Analog Model (Verilog-A) Mechanical Model (Verilog-A) Abstract System Model (Verilog-AMS:VerilogandVerilog-A) Digital Library Process Library Tapeout Digital Domain Analog Domain Mechanical Domain Cross-Domain Verification (Verilogwith updatedVerilog-A fromparasiticsand/orVerilogandVerilog-A with Primitives) Cross-Domain Verification (Verilogwith updatedVerilog-A with interconnectparasitics) Analog Macro Parasitic Extraction (IC Tool) Extraction, Timing (Timing Tool) Digital MacroMechanical Macro Parasitic Extraction (IC Tool) Custom Analog Design (SPICE) Mechanical Design (Finite Element) Macro Place and Route, Layout Verification: DRC, LVS (APR and IC Tool) Layout Parasitic Extraction (LPE) andBackannotation (IC Tool) Synthesis/APR/Timing (Synthesis Tool) Physical Design/Verif. (IC Tool) Physical Design/Verif. (IC Tool) Digital Model (Verilog) Behavioral Verification (Verilog) MotivationMicrosystemsBottom-UpMicrocontrollerFrameworkTop-DownGaps & Solns.Conclusions

21 Michael S. McCorquodale University of Michigan Top-Down Design Methodology Cross-Domain Verification (Verilogwith updatedVerilog-A from achieved performance and/orVerilogandVerilog-A with Primitives) Analog Model (Verilog-A) Mechanical Model (Verilog-A) Abstract System Model (Verilog-AMS:VerilogandVerilog-A) Digital Library Process Library Tapeout Digital Domain Analog Domain Mechanical Domain Cross-Domain Verification (Verilogwith updatedVerilog-A fromparasiticsand/orVerilogandVerilog-A with Primitives) Cross-Domain Verification (Verilogwith updatedVerilog-A with interconnectparasitics) Analog Macro Parasitic Extraction (IC Tool) Extraction, Timing (Timing Tool) Digital MacroMechanical Macro Parasitic Extraction (IC Tool) Custom Analog Design (SPICE) Mechanical Design (Finite Element) Macro Place and Route, Layout Verification: DRC, LVS (APR and IC Tool) Layout Parasitic Extraction (LPE) andBackannotation (IC Tool) Synthesis/APR/Timing (Synthesis Tool) Physical Design/Verif. (IC Tool) Physical Design/Verif. (IC Tool) Digital Model (Verilog) Behavioral Verification (Verilog) MotivationMicrosystemsBottom-UpMicrocontrollerFrameworkTop-DownGaps & Solns.Conclusions

22 Michael S. McCorquodale University of Michigan Gaps and Solutions Gaps in the Tool Suite MEMS and analog simulation results not automatically extracted to behavioral model Lack of physical verification for MEMS components No synthesis capabilities for MEMS and analog subsystems from topological or behavioral models Inability to port designs between process technologies Solutions: Future Direction Custom and manual extraction: Requires design automation Custom mod. of DRC/LVS decks: Requires support No current solution: Requires design automation MotivationMicrosystemsBottom-UpMicrocontrollerFrameworkTop-DownGaps & Solns.Conclusions

23 Michael S. McCorquodale University of Michigan Conclusions Microsystem design methodologies are in their infancy Current methodologies have originated from the disparate nature of the technology The proposed top-down methodology leverages advances in mixed-signal design automation The proposed methodology is efficient and offers superior verification as compared to current methodologies Gaps in tool suites exist and must be addressed for future microsystems developments Tool suites are disparate and can be built into a single framework MotivationMicrosystemsBottom-UpMicrocontrollerFrameworkTop-DownGaps & Solns.Conclusions